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參數(shù)資料
| 型號： | 29W040 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 4 Mbit 512Kb x8, Uniform Block Low Voltage Single Supply Flash Memory |
| 中文描述： | 4兆位512KB的× 8，統(tǒng)一座低電壓單電源閃存 |
| 文件頁數(shù)： | 4/31頁 |
| 文件大?。?/td> | 205K |
| 代理商： | 29W040 |
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Operation
E
G
W
DQ0 - DQ7
Read
V
IL
V
IL
V
IH
Data Output
Write
V
IL
V
IH
V
IL
Data Input
Output Disable
V
IL
V
IH
V
IH
Hi-Z
Standby
V
IH
X
X
Hi-Z
Note:
X = V
IL
or V
IH
Table3. Operations
Code
E
G
W
A0
A1
A6
A9
Other
Addresses
DQ0 - DQ7
Manufact. Code
V
IL
V
IL
V
IH
V
IL
V
IL
V
IL
V
ID
Don’t Care
20h
Device Code
V
IL
V
IL
V
IH
V
IH
V
IL
V
IL
V
ID
Don’t Care
E3h
Table4. ElectronicSignature
Code
E
G
W
A0
A1
A6
A16
A17
A18
Other
Addresses
DQ0 - DQ7
Protected Block
V
IL
V
IL
V
IH
V
IL
V
IH
V
IL
SA
SA
SA
Don’t Care
01h
Unprotected Block
V
IL
V
IL
V
IH
V
IL
V
IH
V
IL
SA
SA
SA
Don’t Care
00h
Note:
SA= Address of block beingchecked
Table5. BlockProtectionStatus
DEVICEOPERATION
Signal Descriptions
AddressInputs (A0-A18).
Theaddress inputs for
thememory arrayarelatchedduring awriteopera-
tion. The A9 address input is used also for the
Electronic Signatureread and BlockProtect veri-
fication. When A9 is raised to V
ID
, either a Read
Manufacturer Code, Read Device Code or Verify
BlockProtectionisenableddependingon thecom-
bination of levelson A0, A1 and A6. When A0, A1
and A6areLow,the ElectronicSignatureManufac-
turercodeis read,when A0is Highand A1and A6
are Low,the Device code is read, and when A1 is
High and A0 and A6 are low, the BlockProtection
Status with protect/unprotectalgorithm is read for
the blockaddressedbyA16, A17, A18.
Data Input/Outputs(DQ0-DQ7).
Thedata inputis
a byteto be programmed or a commandwrittento
the C.I. Both are latchedwhen ChipEnable E and
WriteEnableW areactive.The dataoutput isfrom
the memory Array, the Electronic Signature, the
Data Polling bit (DQ7), the Toggle Bit (DQ6), the
Error bit (DQ5) or the Erase Timer bit (DQ3). Ou-
puts are valid when Chip Enable E and Output
EnableG are active.The outputis highimpedance
when the chip is deselected or the outputs are
disabled.
Chip Enable (E).
The Chip Enable activates the
memory control logic, input buffers, decoders and
senseamplifiers.EHighdeselectsthememoryand
reduces the power consumption to the standby
level. E can also be used to control writing to the
command registerand to the memoryarray, while
W remains at a low level. Addresses are then
latchedon thefallingedgeofEwhiledataislatched
on the rising edge of E. The Chip Enable must be
forcedto V
ID
during Block Unprotect operations.
Output Enable (G).
The Output Enable gates the
outputs through the data buffers during a read
operation. G must be forced to V
ID
level during
BlockProtect and Block Unprotectoperations.
WriteEnable(W).
Thisinputcontrolswritingto the
CommandRegisterandAddressandDatalatches.
Addressesarelatchedon thefallingedgeofW,and
Data Inputs are latched on the rising edge of W.
V
CC
Supply Voltage.
The power supply for all
operations(Read, Programand Erase).
V
SS
Ground.
V
SS
is the reference for all voltage
measurements.
4/31
M29W040
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