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參數(shù)資料
| 型號： | 29LV040C-70 |
| 廠商： | Macronix International Co., Ltd. |
| 英文描述： | 4M-BIT [512K x 8] CMOS SINGLE VOLTAGE 3V ONLY EQUAL SECTOR FLASH MEMORY |
| 中文描述： | 4分位[為512k × 8] CMOS單電壓3V只等于部門閃存 |
| 文件頁數(shù)： | 15/52頁 |
| 文件大?。?/td> | 499K |
| 代理商： | 29LV040C-70 |
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15
P/N:PM1149
MX29LV040C
REV. 1.3, APR. 24, 2006
If Data# Polling or the Toggle Bit indicates the device has
been written with a valid erase command, Q3 may be
used to determine if the sector erase timer window is
still open. If Q3 is high ("1") the internally controlled
erase cycle has begun; attempts to write subsequent
commands to the device will be ignored until the erase
operation is completed as indicated by Data# Polling or
Toggle Bit. If Q3 is low ("0"), the device will accept
additional sector erase commands. To insure the com-
mand has been accepted, the system software should
check the status of Q3 prior to and following each sub-
sequent sector erase command. If Q3 were high on the
second status check, the command may not have been
accepted.
DATA PROTECTION
The MX29LV040C is designed to offer protection against
accidental erasure or programming caused by spurious
system level signals that may exist during power transi-
tion. During power up the device automatically resets
the state machine in the Read mode. In addition, with
its control register architecture, alteration of the memory
contents only occurs after successful completion of spe-
cific command sequences. The device also incorpo-
rates several features to prevent inadvertent write cycles
resulting from VCC power-up and power-down transition
or system noise.
LOW VCC WRITE INHIBIT
When VCC is less than VLKO the device does not ac-
cept any write cycles. This protects data during VCC
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until VCC
is greater than VLKO. The system must provide the proper
signals to the control pins to prevent unintentional write
when VCC is greater than VLKO.
WRITE PULSE "GLITCH" PROTECTION
Noise pulses of less than 5ns(typical) on CE# or WE#
will not initiate a write cycle.
LOGICAL INHIBIT
Writing is inhibited by holding any one of OE# = VIL,
CE# = VIH or WE# = VIH. To initiate a write cycle CE#
and WE# must be a logical zero while OE# is a logical
one.
POW
ER SUPPLY DECOUPLING
In order to reduce power switching effect, each device
should have a 0.1uF ceramic capacitor connected be-
tween its VCC and GND.
POWER-UP SEQUENCE
The MX29LV040C powers up in the Read only mode. In
addition, the memory contents may only be altered after
successful completion of the predefined command se-
quences.
SECTOR PROTECTION
The MX29LV040C features hardware sector protection.
This feature will disable both program and erase opera-
tions for these sectors protected. To activate this mode,
the programming equipment must force VID on address
pin A9 and OE# (suggest VID = 12V). Programming of
the protection circuitry begins on the falling edge of the
WE# pulse and is terminated on the rising edge. Please
refer to sector protect algorithm and waveform.
To verify programming of the protection circuitry, the pro-
gramming equipment must force VID on address pin A9
( with CE# and OE# at VIL and WE# at VIH). When
A1=VIH, A0=VIL, A6=VIL, it will produce a logical "1"
code at device output Q0 for a protected sector. Other-
wise the device will produce 00H for the unprotected sec-
tor. In this mode, the addresses, except for A1, are don't
care. Address locations with A1 = VIL are reserved to
read manufacturer and device codes.(Read Silicon ID)
It is also possible to determine if the sector is protected
in the system by writing a Read Silicon ID command.
Performing a read operation with A1=VIH, it will produce
a logical "1" at Q0 for the protected sector.
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| 29LV040C-90 | 制造商:MCNIX 制造商全稱:Macronix International 功能描述:4M-BIT [512K x 8] CMOS SINGLE VOLTAGE 3V ONLY EQUAL SECTOR FLASH MEMORY |
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