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參數(shù)資料
| 型號(hào)： | 29C516E |
| 廠商： | ATMEL CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | 97-3106A14S-5S |
| 中文描述： | CMOS SERIES, 16-BIT ERROR DETECT AND CORRECT CKT, PQFP100 |
| 封裝： | MQFL-100 |
| 文件頁數(shù)： | 10/16頁 |
| 文件大?。?/td> | 94K |
| 代理商： | 29C516E |
29C516E
10
Rev. D (09 Dec. 97)
Table 8:
T
U
C
S
R
E
M
R
E
M
C
N
Function
1
1
UD1
[
0..15
]
= MD
[
0..15
]
UD1
[
0..15
]
=
{
corrected MD
[
0..15
]}
UD1
[
0..15
]
=
{
corrupted MD
[
0..15
]}
UD1
[
0..15
]
= MD
[
0..15
]
UD1
[
0..15
]
=
{
MC
[
0..7
]
Syndrome
}
UD1
[
0..15
]
= H.Z
UD2
[
0..15
]
=
{
expected UD1
[
0..15
]}
(User 2 listening)
UD2
[
0..15
]
= MD
[
0..15
]
UD2
[
0..15
]
=
{
corrected MD
[
0..15
]}
UD2
[
0..15
]
=
{
corrupted MD
[
0..15
]}
UD2
[
0..15
]
= MD
[
0..15
]
UD2
[
0..15
]
=
{
MC
[
0..7
]
Syndrome
}
UD2
[
0..15
]
= H.Z
1
1
1
0
0
x
x
x
0
1
x
0
1
0
0
1
1
0
0
x
x
x
x
x
x
0
1
1
x
x
x
x
x
x
x
x
x
1
1
x
x
1
0
0
x
x
1
1
1
1
x
x
x
1
0
0
0
1
x
0
1
1
0
1
x
x
x
1
0
0
x
x
x
0
x
x
x
1
1
x
x
x
x
x
x
1
1
0
0
1
x
x
x
x
UD1
[
0..15
]
=
{
expected UD2
[
0..15
]}
(User 1 listening)
x : don’t care
9.2. Memory Write
The TRANS pin is driven at a high level to select the
access to the memory. The external arbiter drives the
U2/U1 pin and dispatches the commands RD/WRx,
MEMx and ENx. All transaction managed by the master
user can be listened by the second user.
Table 9:
T
U
R
E
M
R
E
M
Function
0
0
0
x
x
x
MD
[
0..15
]
= UD1
[
0..15
]
MC
[
0..7
]
=
{
check–bits generated from UD1
[
0..15
]}
MD
[
0..15
]
= H.Z
MC
[
0..7
]
= H.Z
UD2
[
0..15
]
= UD1
[
0..15
]
(User 2 listening)
MD
[
0..15
]
= UD2
[
0..15
]
MC
[
0..7
]
=
{
check–bits generated from UD2
[
0..15
]}
MD
[
0..15
]
= H.Z
MC
[
0..7
]
= H.Z
UD1
[
0..15
]
= UD2
[
0..15
]
(User 1 listening)
1
0
0
1
x
x
x
x
x
1
0
x
x
1
0
0
x
x
x
0
0
0
1
1
x
x
x
0
1
x
x
1
1
0
0
0
x
x
x : don’t care
CERR and NCERR are not valid
CORRECT and SYNCHK are not active
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