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參數(shù)資料
| 型號： | 29C256 |
| 廠商： | Atmel Corp. |
| 英文描述： | 256K 32K x 8 5-volt Only CMOS Flash Memory |
| 中文描述： | 256K 32K的× 8 5伏只有閃存的CMOS |
| 文件頁數(shù)： | 2/17頁 |
| 文件大?。?/td> | 343K |
| 代理商： | 29C256 |
2
AT29C256
0046P–FLASH–10/04
To allow for simple in-system reprogrammability, the AT29C256 does not require high
input voltages for programming. Five-volt-only commands determine the operation of
the device. Reading data out of the device is similar to reading from a static RAM.
Reprogramming the AT29C256 is performed on a page basis; 64 bytes of data are
loaded into the device and then simultaneously programmed. The contents of the entire
device may be erased by using a six-byte software code (although erasure before pro-
gramming is not needed).
During a reprogram cycle, the address locations and 64 bytes of data are internally
latched, freeing the address and data bus for other operations. Following the initiation of
a program cycle, the device will automatically erase the page and then program the
latched data using an internal control timer. The end of a program cycle can be detected
by DATA polling of I/O7. Once the end of a program cycle has been detected a new
access for a read, program or chip erase can begin.
Block Diagram
Device Operation
READ:
WE is high, the data stored at the memory location determined by the address pins
is asserted on the outputs. The outputs are put in the high impedance state whenever
CE or OE is high. This dual-line control gives designers flexibility in preventing bus
contention.
The AT29C256 is accessed like a static RAM. When CE and OE are low and
BYTE LOAD:
with CE or WE low (respectively) and OE high. The address is latched on the falling
edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of
CE or WE. Byte loads are used to enter the 64 bytes of a page to be programmed or the
software codes for data protection and chip erasure.
A byte load is performed by applying a low pulse on the WE or CE input
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