參數(shù)資料
型號: 293D107X9010D2T
廠商: Vishay Intertechnology,Inc.
英文描述: Solid Tantalum Chip Capacitors TANTAMOUNT, Commercial, Surface Mount
中文描述: 固體鉭電容器芯片無異,商業(yè),表面貼裝
文件頁數(shù): 10/13頁
文件大?。?/td> 160K
代理商: 293D107X9010D2T
www.vishay.com
24
293D
Vishay Sprague
Document Number 40002
Revision 27-Oct-04
For technical questions, contact tantalum@vishay.com
12.
Shock Test:
12.1
Capacitors shall be rigidly mounted by means of
suitable brackets. The test load shall be distributed
uniformly on the test platform to minimize the effects
of unbalanced loads.
12.1.1
Test equipment shall be adjusted to produce a shock
of 100 g peak with the duration of 6 mS and sawtooth
waveform at a velocity change of 9.7 ft./sec.
12.2
Capacitors shall be subjected to 3 shocks applied in
each of 3 directions corresponding to the 3 mutually
perpendicular axes of the capacitors.
12.3
Rated DC voltage shall be applied during test.
12.3.1
An oscilloscope or other comparable means shall be
used in determining electrical intermittency during
tests. The replacement voltage applied shall not
exceed 2 volts rms.
12.4
Electrical tests shall show no evidence of intermittent
contacts, open circuits or short circuits during these
tests.
12.5
There shall be no mechanical damage to these
capacitors as a result of these tests.
12.6
Following the shock test, capacitors shall meet the
original limits for capacitance, dissipation factor and l
leakage current.
13.
Moisture Resistance:
13.1
Capacitors shall be subjected to temperature cycling
at 90% to 95% relative humidity, from + 25
°
C to
+65
°
C to + 25
°
C (+ 10
°
C, - 2
°
C) over a period of 8
hours per cycle for 1000 hours.
13.2
Following the moisture resistance test, the leakage
current and dissipation factor shall meet the initial
requirements, and the change in capacitance shall
not exceed
±
10%.
14.
Thermal Shock:
14.1
Capacitors shall be conditioned prior to temperature
cycling for 15 minutes at + 25
°
C, at less than 50%
relative humidity and a barometric pressure at 28 to 31"
14.2
Capacitors shall be subjected to thermal shock in a
cycle of exposure to ambient air at :
- 55
°
C (+ 0
°
C,- 5
°
C) for 30 minutes, then
+ 25
°
C (+10
°
C, - 5
°
C) for 5 minutes, then
PERFORMANCE CHARACTERISTICS
(Continued)
+ 125
°
C (+ 3
°
C, - 0
°
C) for 30 minutes, then
+ 25
°
C (+ 10
°
C, - 5
°
C) for 5 minutes for 5 cycles.
14.3
Capacitors shall show no evidence of harmful or
extensive corrosion, obliteration of marking or
other visible damage.
14.4
Following the thermal shock test, capacitors shall
meet the original requirements for leakage current and
dissipation factor. Capacitance change shall not
exceed
±
5% of the original measured value.
15.
Soldering Compatibility
:
15.1
Resistance to Solder Heat:
Capacitors will
withstand exposure to + 260
°
C + 5
°
C for 10 seconds.
15.1.1
Following the resistance to soldering heat test,
capacitance, dissipation factor and DC leakage
current shall meet the initial requirement.
15.2
Solderability:
Capacitors will meet the solderability
requirements of ANSI/J-STD-002, Test B (MIL-STD-
202, method and test S.)
16.
Terminal Strength:
Per UEC-384-3, minimum of
5N shear force.
17.
Environmental:
Mercury, CFC and ODS materials
are not used in the manufacture of these capacitors.
18.
Flammability:
Encapsulant materials meet UL94 V0
with an oxygen index of 32%.
19.
Capacitor Failure Mode:
The predominant failure
mode for solid tantalum capacitors is increased
leakage current resulting in a shorted circuit. Capaci-
tor failure may result from excess forward or reverse
DC voltage, surge current, ripple current, thermal
shock or excessive temperature.
The increase in leakage is caused by a breakdown of
the Ta
2
O
5
dielectric. For additional information on
leakage failure of solid tantalum chip capacitors, refer
to Vishay Sprague Technical Paper,
Leakage Failure
Mode in Solid Tantalum Chip Capacitors.
20.
Surge Current:
All D and E case code 293D
capacitors are 100% surge current tested at + 25
°
C
and rated voltage. The total series circuit resistance
is 0.5 ohms. Each charge cycle of 0.10 seconds is
followed by a discharge cycle of 0.10 seconds. Three
surge cycles are applied. Each capacitor is tested
individually to maximize the peak charging current.
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