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參數(shù)資料
| 型號： | 29109BRA |
| 廠商： | INTERSIL CORP |
| 元件分類： | Static RAM |
| 英文描述： | 16K X 1 STANDARD SRAM, 70 ns, CDIP20 |
| 封裝： | CERAMIC, DIP-20 |
| 文件頁數(shù)： | 1/1頁 |
| 文件大?。?/td> | 141K |
| 代理商： | 29109BRA |
1
TM
March 1997
HM-65262
16K x 1 Asynchronous
CMOS Static RAM
Features
Fast Access Time . . . . . . . . . . . . . . . . . . . 70/85ns Max
Low Standby Current. . . . . . . . . . . . . . . . . . . . 50
A Max
Low Operating Current . . . . . . . . . . . . . . . . . 50mA Max
Data Retention at 2.0V . . . . . . . . . . . . . . . . . . . 20
A Max
TTL Compatible Inputs and Outputs
JEDEC Approved Pinout
No Clocks or Strobes Required
Temperature Range . . . . . . . . . . . . . . . +55oC to +125oC
Equal Cycle and Access Time
Single 5V Supply
Gated Inputs-No Pull-Up or Pull-Down Resistors
Required
Description
The HM-65262 is a CMOS 16384 x 1-bit Static Random
Access Memory manufactured using the Intersil Advanced
SAJI V process. The device utilizes asynchronous circuit
design for fast cycle times and ease of use. The HM-65262
is available in both JEDEC standard 20 pin, 0.300 inch wide
CERDIP and 20 pad CLCC packages, providing high board-
level packing density. Gated inputs lower standby current,
and also eliminate the need for pull-up or pull-down resis-
tors.
The HM-65262, a full CMOS RAM, utilizes an array of six
transistor (6T) memory cells for the most stable and lowest
possible standby supply current over the full military temper-
ature range. In addition to this, the high stability of the 6T
RAM cell provides excellent protection against soft errors
due to noise and alpha particles. This stability also improves
the radiation tolerance of the RAM over that of four transistor
(4T) devices.
Pinouts
Ordering Information
PACKAGE
TEMP. RANGE
70ns/20
A (NOTE 1) 85ns/20A (NOTE 1)
(NOTE 1)
85ns/400
A
PKG. NO.
CERDIP
-40oC to +85oC
HM1-65262B-9
HM1-65262-9
-
F20.3
JAN #
-55oC to +125oC
29109BRA
29103BRA
-
F20.3
SMD#
-55oC to +125oC
8413203RA
8413201RA
-
F20.3
CLCC (SMD#)
-55oC to +125oC
8413203YA
8413201YA
-
J20.C
NOTE:
1. Access Time/Data Retention Supply Current.
HM-65262 (CERDIP)
TOP VIEW
HM-65262 (CLCC)
TOP VIEW
11
12
13
14
15
16
17
18
20
19
10
9
8
7
6
5
4
3
2
1
A0
A1
A2
A3
A4
A5
Q
A6
W
GND
VCC
A12
A11
A10
A13
A9
A8
A7
D
E
3
4
5
6
7
910 11 12
220
119
8
15
14
18
17
16
13
A0
A1
A2
V
CC
A1
3
A3
A4
A5
A6
Q
A12
A11
A10
A9
A8
A7
W
GN
D
E
D
A0 - A13
Address Input
E
Chip Enable/Power Down
Q
Data Out
D
Data In
VSS/GND
Ground
VCC
Power (+5)
W
Write Enable
FN3002.2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
| Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2002. All Rights Reserved
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