參數資料
型號: 28F800B5
英文描述: Dual-Slot, PCMCIA Analog Power Controller
中文描述: 智能5引導塊。閃存系列2。 4。 8兆比特
文件頁數: 27/44頁
文件大?。?/td> 496K
代理商: 28F800B5
28F400BL-T/B, 28F004BL-T/B
290450–13
Bus
Command
Comments
Operation
Write
Setup
Erase
Data
e
20H
Address
e
Within block to be
erased
Write
Erase
Data
e
D0H
Address
e
Within block to be
erased
Read
Status Register Data.
Toggle OE
Y
or CE
Y
to update
Status Register
Standby
Check SR.7
1
e
Ready, 0
e
Busy
Repeat for subsequent blocks.
Full status check can be done after each block or after a
sequence of blocks.
Write FFH after the last block erase operation to reset the
device to Read Array Mode.
Full Status Check Procedure
290450–14
Bus
Command
Comments
Operation
Standby
Check SR.3
1
e
V
PP
Low Detect
Standby
Check SR.4,5
Both 1
e
Command Sequence
Error
Standby
Check SR.5
1
e
Block Erase Error
SR.3 MUST be cleared, if set during an erase attempt,
before further attempts are allowed by the Write State
Machine.
SR.5 is only cleared by the Clear Status Register
Command, in cases where multiple blocks are erased
before full status is checked.
If error is detected, clear the Status Register before
attempting retry or other error recovery.
Figure 14. Automated Block Erase Flowchart
27
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