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參數(shù)資料
| 型號： | 28F008SC |
| 廠商： | Intel Corp. |
| 英文描述： | 8-MBIT SmartVoltage FlashFile Memory(8M位智能電壓閃速存儲器) |
| 中文描述： | 8兆SmartVoltage FlashFile內(nèi)存（800萬位智能電壓閃速存儲器） |
| 文件頁數(shù)： | 7/42頁 |
| 文件大小： | 725K |
| 代理商： | 28F008SC |
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E
BYTE-WIDE SmartVoltage FlashFile MEMORY FAMILY
7
PRELIMINARY
4-Mbit: A - A ,
8-Mbit: A - A ,
16-Mbit: A - A
18
Input
Buffer
Output
Buffer
Identifier
Register
Status
Register
Command
Register
I/O Logic
CoData
Input
Buffer
Address
Latch
Address
Counter
Y
Decoder
X
Decoder
Y Gating
4-Mbit: Eight
8-Mbit: Sixteen
16-Mbit: Thirty-Two
64-Kbyte Blocks
Write State
Machine
Program/Erase
Voltage Switch
CE#
WE#
OE#
RP#
RY/BY#
V
V
GND
DQ - DQ
PP
V
CC
7
Figure 1. Block Diagram
Table 2. Pin Descriptions
Sym
Type
Name and Function
A
0
–A
20
INPUT
ADDRESS INPUTS:
Inputs for addresses during read and write operations.
Addresses are internally latched during a write cycle.
4 Mbit
→
A
0
–A
18
8 Mbit
→
A
0
–A
19
16 Mbit
→
A
0
–A
20
DATA INPUT/OUTPUTS:
Inputs data and commands during CUI write cycles;
outputs data during memory array, status register, and identifier code read cycles.
Data pins float to high-impedance when the chip is deselected or outputs are
disabled. Data is internally latched during a write cycle.
DQ
0
–DQ
7
INPUT/
OUTPUT
CE#
INPUT
CHIP ENABLE:
Activates the device’s control logic, input buffers, decoders, and
sense amplifiers. CE#-high deselects the device and reduces power consumption to
standby levels.
RP#
INPUT
RESET/DEEP POWER-DOWN:
When driven low, RP# inhibits write operations
which provides data protection during power transitions, puts the device in deep
power-down mode, and resets internal automation. RP#-high enables normal
operation. Exit from deep power-down sets the device to read array mode.
RP# at V
HH
enables setting of the master lock-bit and enables configuration of block
lock-bits when the master lock-bit is set. RP# = V
HH
overrides block lock-bits,
thereby enabling block erase and program operations to locked memory blocks.
Block erase, program, or lock-bit configuration with V
IH
< RP# < V
HH
produce
spurious results and should not be attempted.
OE#
INPUT
OUTPUT ENABLE:
Gates the device’s outputs during a read cycle.
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