參數(shù)資料
型號(hào): 28F004B5
英文描述: IEEE 802.3af Power-Over-Ethernet Interface/PWM Controller for Power Devices
中文描述: 智能5引導(dǎo)塊。閃存系列2。 4。 8兆比特
文件頁(yè)數(shù): 41/44頁(yè)
文件大?。?/td> 496K
代理商: 28F004B5
28F400BL-T/B, 28F004BL-T/B
AC CHARACTERISTICS FOR CE
Y
-CONTROLLED WRITE OPERATIONS
V
CC
e
3.15V–3.6V, 5.0V
g
10%
Versions
28F400BL-150
28F004BL-150
Unit
Symbol
Parameter
Notes
Min
Max
t
AVAV
t
WC
Write Cycle Time
150
ns
t
PHEL
t
PS
RP
Y
High Recovery to
CE
Y
Going Low
1.0
m
s
t
WLEL
t
WS
WE
Y
Setup to CE
Y
Going Low
0
ns
t
PHHEH
t
PHS
RP
Y
V
HH
Setup to CE
Y
Going High
V
PP
Setup to CE
Y
Going High
Address Setup to CE
Y
Going High
6, 8
200
ns
t
VPEH
t
VPS
5, 8
200
ns
t
AVEH
t
AS
3
95
ns
t
DVEH
t
DS
Data Setup to CE
Y
Going High
4
100
ns
t
ELEH
t
CP
CE
Y
Pulse Width
100
ns
t
EHDX
t
DH
Data Hold from CE
Y
High
4
0
ns
t
EHAX
t
AH
Address Hold from CE
Y
High
3
10
ns
t
EHWH
t
WH
WE
Y
Hold from CE
Y
High
10
ns
t
EHEL
t
CPH
CE
Y
Pulse Width High
50
ns
t
EHQV1
Duration of Programming
Operation Word/Byte
2, 5, 6
6
m
s
t
EHQV2
Duration of Erase Operation (Boot)
2, 5, 6
0.3
s
t
EHQV3
Duration of Erase
Operation (Parameter)
2, 5, 6
0.3
s
t
EHQV4
Duration of Erase Operation (Main)
2, 5, 6
0.6
s
t
QVVL
t
VPH
V
PP
Hold from Valid SRD
RP
Y
V
HH
Hold from Valid SRD
5, 8
0
ns
t
QVPH
t
PPH
6, 8
0
ns
t
PHBR
Boot-Block Relock Delay
7, 8
200
ns
t
IR
Input Rise Time
10
ns
t
IF
Input Fall Time
10
ns
NOTES:
1. Chip-Enable Controlled Writes: Write operations are driven by the valid combination of CE
Y
and WE
Y
in systems where
CE
Y
defines the write pulse-width (within a longer WE
Y
timing waveform), all set-up, hold and inactive WE
Y
times
should be measured relative to the CE
Y
waveform.
2, 3, 4, 5, 6, 7, 8. Refer to AC Characteristics for WE
Y
-Controlled Write operations.
9. Read timing characteristics during write and erase operations are the same as during read-only operations. Refer to AC
Characteristics during Read Mode.
41
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