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| 型號(hào)： | 27174A |
| 英文描述： | Versatile I/0: DQ--VI/O and Enhanced--VI/O |
| 中文描述： | 通用的I / 0：宿舍-六/ O和增強(qiáng)-六/輸出 |
| 文件頁數(shù)： | 4/4頁 |
| 文件大?。?/td> | 67K |
| 代理商： | 27174A |
Versatile I/O: DQ–V
I/O
and Enhanced–V
I/O
Figure 3.
I/O Signaling to Enhanced–V
IO
3V Flash with V
IO
= 1.8V
As shown in Figure 3, all the signals on the microcon-
troller and Flash can be directly connected together
without the need of voltage translation buffers.
Without the need for translation buffers, data skew is
no longer a significant problem even if the microcon-
troller does not assert the address and control lines
before the data lines. The chip count and power con-
sumption the circuit in Figure 3 has been reduced, from
that of Figure 1, and the board space required and lay-
out complexity have been significantly reduced.
Voltage Range Limitations
Even though Versatile I/O expands the voltage range of
AMD’s Flash memories, the range is limited to (unless
otherwise stated in the datasheet) the JEDEC standard
voltage range given by the voltage on the V
I/O
pin(s).
For example, if a 3.0V Versatile I/O Flash is used and
1.8V is being applied to the V
I/O
pin(s), applying 3.0V
signals to the Flash device’s I/O will damage the mem-
ory. In order to use 3.0V signals, the voltage applied to
the V
I/O
pin(s) must be supplied at 3.0V. This limitation
does not prevent the user from using multiple voltage
levels when communicating with the Flash memory, it
simply requires that the V
I/O
pin(s) be set to the appro-
priate voltage.
Conclusion
AMD’s Versatile I/O allows the designer to reduce cost,
chip count, complexity and debug time on designs by
eliminating the need for voltage translation buffers and
the effects the buffers will have on signal integrity. In
addition, designs can be upgraded from 3.0V systems
to 2.5V or even 1.8V systems without the need to
requalify a new Flash device.
MicroController
Vcc = 1.8v
Address
Data
Control
Enhanced-V
I/O
3v Flash
with V
I/O
= 1.8v
Other 1.8v
Devices
32
16
8
16
8
24
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