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參數(shù)資料
| 型號： | 26CV12 |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | High Performance E2CMOS PLD Generic Array Logic |
| 中文描述： | E2CMOS的可編程邏輯器件的高性能通用陣列邏輯 |
| 文件頁數(shù)： | 11/17頁 |
| 文件大?。?/td> | 255K |
| 代理商： | 26CV12 |
Specifications
GAL26CV12
11
f
max with Internal Feedback 1/(
t
su+
t
cf)
Note:
f
max with external feedback is cal-
culated from measured
t
su and
t
co.
f
max with External Feedback 1/(
t
su+
t
co)
Note:
t
cf is a calculated value, derived by sub-
tracting
t
su from the period of fmax w/internal
feedback (
t
cf = 1/
f
max -
t
su). The value of
t
cf is
used primarily when calculating the delay from
clocking a register to a combinatorial output
(through registered feedback), as shown above.
For example, the timing from clock to a combi-
natorial output is equal to
t
cf +
t
pd.
f
max with No Feedback
Note:
f
max with no feedback may be less
than 1/(
t
wh +
t
wl). This is to allow for a
clock duty cycle of other than 50%.
GAL26CV12 Output Load Conditions (see figure)
Test Condition
R
1
R
2
C
L
A
B
300
∞
300
∞
300
390
390
390
390
390
50pF
50pF
50pF
5pF
5pF
Active High
Active Low
Active High
Active Low
C
TEST POINT
C *
L
FROM OUTPUT (O/Q)
UNDER TEST
+5V
*C
L
INCLUDES TEST FIXTURE AND PROBE CAPACITANCE
R
2
R
1
REGISTER
LOGIC
ARRAY
t
co
t
su
CL K
Input Pulse Levels
Input Rise and
Fall Times
GND to 3.0V
1.5ns 10%
–
90%
3ns 10%
–
90%
C-7/-10/-15
B-10/-15/-20
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
1.5V
1.5V
See Figure
3-state levels are measured 0.5V from steady-state active
level.
REGISTER
LOGIC
ARRAY
CLK
t
su +
t
h
CLK
REGISTER
LOGIC
ARRAY
t
cf
t
pd
f
max Definitions
Switching Test Conditions
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