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| 型號： | 25267B |
| 英文描述： | Interfacing Motorola＇s MPC56x Microcontroller to AMD＇s Am29BDD160G Flash Memory |
| 中文描述： | 接口摩托羅拉MPC56x單片機AMD的Am29BDD160G閃存 |
| 文件頁數(shù)： | 4/11頁 |
| 文件大?。?/td> | 153K |
| 代理商： | 25267B |
Interfacing Motorola’s MPC56x Microcontroller to AMD’s Am29BDD160G Flash Memory
3
Table 7. Am29BDD160GB Flash Configuration Register
The following parameters need to be modified in the
Configuration Register by using Configuration Register
write commands while the Embedded Algorithm (a pro-
gram or erase operation) is not active. The RM bit must
be set to zero to enable synchronous burst operations.
Bits BS and BL needs to be set accordingly for linear or
interleaved burst and to determine the number of cy-
cles per burst respectively. Bit definitions that need to
be modified are as follows:
For example, assume that a controller is in Continuous
Linear Burst with a Burst Initial Access Delay (from the
Flash perspective) of 5 clock cycles and a subsequent
burst access of 1 clock cycle. Also assume that burst
starts from the rising clock edge and the IND/WAIT#
output is asserted during the delay. The Configuration
Register settings are shown in Table 8
.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RM
DS
IAD3
IAD2
IAD1
IAD0
DOC
WC
BS
CC
—
—
—
BL2
BL1
BL0
1
0
0
1
0
1
0
X
X
X
1
0
0
0
X
X
RM
0 for Sync. Burst Reads
1 for Async. Reads
IAD[3:0]
0010b for data valid after 4th rising edge on
next rising edge of clock
BS
0 for Interleaved Burst
1 for Linear Burst
BL[2:0]
Determines the number of consecutive burst
cycles:
001 = 8 byte burst
010 = 16 byte burst
011 = 32 byte burst
100 = 64 byte burst
111 = continuous burst
IAD[3:0]
0000 = 2 CLK Cycle
0001 = 3 CLK Cycle
0010 = 4 CLK Cycle
0011 = 5 CLK Cycle
0100 = 6 CLK Cycle
0101 = 7 CLK Cycle
0110 = 8 CLK Cycle
0111 = 9 CLK Cycle
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