參數(shù)資料
型號(hào): 24LLC02
廠商: Electronic Theatre Controls, Inc.
英文描述: 2K-bit Serial EEPROM for Low Power
中文描述: 的2K位低功耗串行EEPROM
文件頁(yè)數(shù): 11/19頁(yè)
文件大小: 663K
代理商: 24LLC02
HARDWARE-BASED WRITE PROTECTION
You can also write-protect the entire memory area of the 24LLC02. This method of write protection is controlled
by the state of the Write Protect (WP) pin.
When the WP pin is connected to V
CC
, any attempt to write a value to the memory is ignored.
The 24LLC02 will acknowledge slave and word address, but it will not generate an acknowledge after receiving
the first byte of the data. Thus the write cycle will not be started when the stop condition is generated . By
connecting the WP pin to V
SS
, the write function is allowed for the entire memory.
These write protection features effectively change the EEPROM to a ROM in order to prevent data from being
overwritten. Whenever the write function is disabled, a slave address and a word address are acknowledged on
the bus, but data bytes are not acknowledged.
CURRENT ADDRESS BYTE READ OPERATION
The internal word address pointer maintains the address of the last word accessed, incremented by one.
Therefore, if the last access (either read or write) was to the address “n”, the next read operation would access
data at address “n+1”.
When the 24LLC02 receives a slave address with the R /
W
bit set to “1”, it issues an ACK and sends the eight
bits of data.The master does not acknowledge the transfer but it does generate a Stop condition. In this way,
the 24LLC02 effectively stops the transmission (see Figure 1-12).
Slave Address
Data
Start
A
C
K
Stop
N
O
A
C
K
Figure 1-12. Current Address Byte Read Operation
* All specs and applications shown above subject to change without prior notice.
1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C
Tel:886-3-3529445
Fax:886-3-3521052
Email: server@ceramate.com.tw
Http: www.ceramate.com.tw
Page
11 of 19 Rev 1.2 May 6,2002
24LLC02
2K-bit Serial EEPROM for Low Power
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