參數(shù)資料
型號(hào): 24LCS61/ST
元件分類(lèi): PROM
英文描述: 128 X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8
封裝: TSSOP-8
文件頁(yè)數(shù): 13/17頁(yè)
文件大?。?/td> 249K
代理商: 24LCS61/ST
24LCS61/62
1999 Microchip Technology Inc.
Preliminary
DS21226C-page 5
3.5
Acknowledge
Each receiving device, when addressed, is required to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
The device that acknowledges has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse.
Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the last
byte that has been clocked out of the slave. In this case,
the slave must leave the data line HIGH to enable the
master to generate the STOP condition (Figure 3-2).
FIGURE 3-2:
ACKNOWLEDGE TIMING
Note:
The 24LCS61/62 does not generate any
acknowledge bits if an internal program-
ming cycle is in progress.
SCL
9
8
7
6
5
4
3
2
11
2
3
Transmitter must release the SDA line at this point
allowing the Receiver to pull the SDA line low to
acknowledge the previous eight bits of data.
Receiver must release the SDA line at this point
so the Transmitter can continue sending data.
Data from transmitter
SDA
Acknowledge
Bit
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