參數(shù)資料
型號(hào): 24LCS41
廠商: Microchip Technology Inc.
英文描述: 1K/4K 2.5V Dual Mode, Dual Port IIC Serial EEPROM(1K/4K位,2.5V雙模式,雙端口IIC串行EEPROM)
中文描述: 1K/4K 2.5V的雙模式,雙端口串行EEPROM國(guó)際進(jìn)口證(1K/4K位,2.5V的雙模式,雙端口串行EEPROM的國(guó)際進(jìn)口許可證)
文件頁數(shù): 11/12頁
文件大小: 90K
代理商: 24LCS41
1996 Microchip Technology Inc.
Preliminary
DS21174A-page 11
24LCS41
FIGURE 7-2:
RANDOM READ
FIGURE 7-3:
SEQUENTIAL READ
S
P
S
BUS ACTIVITY
MASTER
MSDA LINE
BUS ACTIVITY
S
T
A
R
T
S
T
O
P
CONTROL
BYTE
WORD
ADDRESS (n)
DATA n
A
C
K
A
C
K
N
O
A
C
K
CONTROL
BYTE
A
C
K
S
T
A
R
T
P
DSDA or
MSDA LINE
BUS ACTIVITY
S
T
O
P
CONTROL
BYTE
DATA n
A
C
K
N
O
A
C
K
A
C
K
A
C
K
A
C
K
DATA n + 1
DATA n + 2
DATA n + X
BUS ACTIVITY
MASTER
8.0
PIN DESCRIPTIONS
8.1
DSDA
This pin is used to transfer addresses and data into and
out of the DDC Monitor Port, when the device is in the
bi-directional Mode. In the Transmit-Only Mode, which
only allows data to be read from the device, data is also
transferred on the DSDA pin. This pin is an open drain
terminal, therefore the DSDA bus requires a pullup
resistor to V
CC
(typical 10K
for 100 kHz, 1K
for 400
kHz).
For normal data transfer in the Bi-directional Mode,
DSDA is allowed to change only during DSCL or MSDA
low. Changes during DSCL high are reserved for indi-
cating the START and STOP conditions.
8.2
DSCL
This pin is the clock input for the DDC Monitor Port
while in the bi-directional Mode, and is used to synchro-
nize data transfer to and from the device. It is also used
as the signaling input to switch the device from the
Transmit-Only Mode to the bi-directional Mode. It must
remain high for the chip to continue operation in the
Transmit-Only Mode.
8.3
VCLK
This pin is the clock input for the DDC Monitor Port
while in the Transmit-Only Mode. In the Transmit-Only
Mode, each bit is clocked out on the rising edge of this
signal. In the bi-directional Mode, a high logic level is
required on this pin to enable write capability.
8.4
DWP
This pin is used for flexible write protection of the DDC
Monitor Port. When the last memory location (7Fh) is
written with any data, this pin is enabled and deter-
mines the write capability of the 24LCS41.
The WP pin has an internal pull up resistor which will
allow write capability (assuming VCLK = 1_ at all times
if this pin is floated.
8.5
MSCL
This pin is the clock input for the Microcontroller Access
Port, and is used to synchronize data transfer to and
from the device.
8.6
MSDA
This pin is used to transfer addresses and data into and
out of the Microcontroller Access Port. This pin is an
open drain terminal, therefore the MSDA bus requires a
pullup resistor to V
CC
(typical 10K
for 100 kHz, 1K
for 400 kHz).
MSDA is allowed to change only during MSCL low.
Changes during MSCL high are reserved for indicating
the START and STOP conditions.
相關(guān)PDF資料
PDF描述
24LCS52 Connectors
24LC52-IP 2K 2.5V I 2 C Serial EEPROM with Software Write Protect
24LC52-ISN 2K 2.5V I 2 C Serial EEPROM with Software Write Protect
24LC52-IST 2K 2.5V I 2 C Serial EEPROM with Software Write Protect
24LC52-P 2K 2.5V I 2 C Serial EEPROM with Software Write Protect
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