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參數(shù)資料
| 型號： | 24LC62-IST |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | 1K/2K Software Addressable I 2 C ⑩ Serial EEPROM |
| 中文描述： | 1K/2K軟件尋址的I 2 C⑩串行EEPROM |
| 文件頁數(shù)： | 3/16頁 |
| 文件大?。?/td> | 426K |
| 代理商： | 24LC62-IST |
24LCS61/62
1997 Microchip Technology Inc.
Preliminary
DS21226A-page 3
TABLE 1-3:
AC CHARACTERISTICS
FIGURE 1-1:
BUS TIMING DATA
All parameters apply across the specified
operating ranges unless otherwise noted.
Vcc = +2.5V to 5.5V
Commercial (C):
Industrial (I):
= 2.5V - 5.5V
STD MODE
Tamb = 0
Tamb = -40
°
°
C to +70
C to +85
°
°
C
C
Parameter
Symbol
V
CC
Vcc = 4.5V - 5.5V
FAST MODE
Units
Remarks
Min.
—
4000
4700
—
—
4000
Max.
100
—
—
1000
300
—
Min.
—
600
1300
—
—
600
Max.
400
—
—
300
300
—
Clock frequency
Clock high time
Clock low time
SDA and SCL rise time
SDA and SCL fall time
START condition hold time
F
T
T
CLK
kHz
ns
ns
ns
ns
ns
HIGH
LOW
T
R
T
F
:
STA
From V
From V
After this period the first
clock pulse is generated
Only relevant for repeated
START condition
(Note 2)
IL
to V
to V
IH
(Note 1)
(Note 1)
IL
IH
T
HD
START condition setup time
T
SU
:
STA
4700
—
600
—
ns
Data input hold time
Data input setup time
STOP condition setup time
Output valid from clock
Bus free time
T
T
T
HD
:
:
:
DAT
0
—
—
—
0
—
—
—
900
—
ns
ns
ns
ns
ns
SU
DAT
250
4000
—
4700
100
600
—
1300
SU
T
T
STO
AA
3500
—
(Note 2)
Time the bus must be free
before a new transmission
can start
(Note 1), C
B
≤
BUF
Output fall time
(from 0.7 V
Input filter spike suppression
(SDA and SCL pins)
Write cycle time
Endurance
CC
to 0.3 V
CC
)
T
OF
—
250
20 +0.1
C
B
—
250
ns
100 pF
T
SP
—
50
50
ns
(Notes 1, 3)
T
WC
—
10M
10
—
—
10M
10
—
ms
Byte or Page mode
cycles 25
°
C, V
Mode (Note 4)
CC
= 5.0V, Block
Note 1:
Not 100% tested. C
As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
The combined T
SP
and V
HYS
specifications are due to Schmitt trigger inputs which provide improved noise
spike suppression. This eliminates the need for a TI specification for standard operation.
This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific
application, please consult the Total Endurance Model which can be obtained on our BBS or website.
B
= total capacitance of one bus line in pF.
2:
3:
4:
SCL
SDA
IN
Tsu:sta
SDA
OUT
T
HD
:
STA
T
LOW
T
HIGH
T
R
T
BUF
T
AA
T
HD
:
DAT
T
SU
:
DAT
T
SU
:
STO
T
SP
T
F
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| 24LC64-E/P | 功能描述:電可擦除可編程只讀存儲(chǔ)器 8kx8 - 2.5V RoHS:否 制造商:Atmel 存儲(chǔ)容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時(shí)鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
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