參數(shù)資料
型號(hào): 24LC52-IP
廠商: Microchip Technology Inc.
元件分類: EEPROM
英文描述: 2K 2.5V I 2 C Serial EEPROM with Software Write Protect
中文描述: 2K 2.5VI 2 C串行EEPROM,帶有軟件寫保護(hù)
文件頁數(shù): 5/12頁
文件大?。?/td> 81K
代理商: 24LC52-IP
1996 Microchip Technology Inc.
Preliminary
DS21166B-page 5
24LCS52
The eighth bit of slave address determines if the master
device wants to read or write to the 24LCS52 (Figure 3-
2). When set to a one a read operation is selected and
when set to a zero a write operation is selected.
FIGURE 3-2:
CONTROL BYTE
ALLOCATION
4.0
WRITE OPERATIONS
4.1
Byte Write
Following the start signal from the master, the device
code(4 bits), the chip select bits (3 bits), and the R/W
bit which is a logic low is placed onto the bus by the
master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will follow
after it has generated an acknowledge bit during the
ninth clock cycle. Therefore the next byte transmitted by
the master is the word address and will be written into
the address pointer of the 24LCS52. After receiving
Operation
Control
Code
1010
1010
0110
Chip
Select
A2 A1 A0
A2 A1 A0
A2 A1 A0
R/W
Read
Write
Set Write Protect
Register
1
0
0
SLAVE ADDRESS
R/W
A
1
0
1
0
A2
A1
A0
START
READ/WRITE
0
1
1
0
A2
A1
A0
OR
another acknowledge signal from the 24LCS52 the
master device will transmit the data word to be written
into the addressed memory location. The 24LCS52
acknowledges again and the master generates a stop
condition. This initiates the internal write cycle, and dur-
ing this time the 24LCS52 will not generate acknowl-
edge signals (Figure 4-1). If an attempt is made to write
to the array when the software or hardware write pro-
tection has been enabled, the device will acknowledge
the command but no data will be written. The write
cycle time must be observed even if the write protection
is enabled.
4.2
Page Write
The write control byte, word address and the first data
byte are transmitted to the 24LCS52 in the same way
as in a byte write. But instead of generating a stop con-
dition, the master transmits up to 15 additional data
bytes to the 24LCS52 which are temporarily stored in
the on-chip page buffer and will be written into the
memory after the master has transmitted a stop condi-
tion. After the receipt of each word, the four lower order
address pointer bits are internally incremented by one.
The higher order four bits of the word address remains
constant. If the master should transmit more than 16
bytes prior to generating the stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the stop condition is received an inter-
nal write cycle will begin (Figure 4-2). If an attempt is
made to write to the array when the hardware write pro-
tection has been enabled, the device will acknowledge
the command but no data will be written. The write
cycle time must be observed even if the write protection
is enabled.
FIGURE 4-1:
BYTE WRITE
FIGURE 4-2:
PAGE WRITE
S
T
A
R
T
S
P
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
A
R
T
S
T
O
P
CONTROL
BYTE
WORD
ADDRESS
DATA
A
C
K
A
C
K
A
C
K
S
P
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
CONTROL
BYTE
WORD
ADDRESS (n)
DATA n
DATA n + 15
S
T
O
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
相關(guān)PDF資料
PDF描述
24LC52-ISN 2K 2.5V I 2 C Serial EEPROM with Software Write Protect
24LC52-IST 2K 2.5V I 2 C Serial EEPROM with Software Write Protect
24LC52-P 2K 2.5V I 2 C Serial EEPROM with Software Write Protect
24LC52-SN 2K 2.5V I 2 C Serial EEPROM with Software Write Protect
24LC52-ST 2K 2.5V I 2 C Serial EEPROM with Software Write Protect
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