參數(shù)資料
型號(hào): 24LC41A
廠商: Microchip Technology Inc.
英文描述: 1K/4K 2.5V Dual Mode, Dual Port IIC Serial EEPROM(1K/4K位,雙模式雙端口,EEPROM)
中文描述: 1K/4K 2.5V的雙模式,雙端口串行EEPROM國際進(jìn)口證(1K/4K位,雙模式雙端口器,EEPROM)
文件頁數(shù): 11/16頁
文件大?。?/td> 106K
代理商: 24LC41A
1996 Microchip Technology Inc.
Preliminary
DS21176A-page 11
24LC41A
6.0
WRITE PROTECTION
6.1
DDC Monitor Port
When using the DDC Monitor Port in the Bi-directional
Mode, the VCLK pin operates as the write protect con-
trol pin. Setting VCLK high allows normal write opera-
tions, while setting VCLK low prevents writing to any
location in the array. Connecting the VCLK pin to V
SS
would allow the monitor port to operate as a serial
ROM, although this configuration would prevent using
the device in the Transmit-Only Mode.
7.0
READ OPERATION
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
slave address is set to one. There are three basic types
of read operations: current address read, random read
and sequential read. These operations are identical for
both the DDC Monitor Port (in Bi-directional Mode) and
the Microcontroller Access Port and are completely
independent of one another.
7.1
Current Address Read
The port contains an address counter that maintains
the address of the last word accessed, internally incre-
mented by one. Therefore, if the previous access (either
a read or write operation) was to address n, the next
current address read operation would access data from
address n + 1. Upon receipt of the slave address with
R/W bit set to one, the port issues an acknowledge and
transmits the 8-bit data word. The master will not
acknowledge the transfer but does generate a stop con-
dition and the port discontinues transmission (see
Figure 7-1).
7.2
Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
port as part of a write operation. After the word address
is sent, the master generates a start condition following
the acknowledge. This terminates the write operation,
but not before the internal address pointer is set. The
master then issues the control byte again, but with
the R/W bit set to a one. The port then issues an
acknowledge and transmits the 8-bit data word. The
master will not acknowledge the transfer but does gen-
erate a stop condition and the port discontinues trans-
mission (see Figure 7-2).
7.3
Sequential Read
Sequential reads are initiated in the same way as a ran-
dom read except that after the port transmits the first
data byte, and the master issues an acknowledge as
opposed to a stop condition in a random read. This
directs the port to transmit the next sequentially
addressed 8-bit word (see Figure 7-3).
To provide sequential reads, the port contains an inter-
nal address pointer, which is incremented by one at the
completion of each operation. This address pointer
allows the entire memory contents to be serially read
during one operation.
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