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參數(shù)資料
| 型號(hào)： | 24LC41A |
| 英文描述： | High-Speed Secure Microcontroller |
| 中文描述： | 24LC41A數(shù)據(jù)表 |
| 文件頁(yè)數(shù)： | 4/18頁(yè) |
| 文件大小： | 244K |
| 代理商： | 24LC41A |
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24LC41A
DS21176D-page 4
2003 Microchip Technology Inc.
2.0
FUNCTIONAL DESCRIPTION
2.1
DDC Monitor Port
The DDC Monitor Port operates in two modes, the
Transmit-only mode and the Bidirectional mode. There
is a separate 2-wire protocol to support each mode,
each having a separate clock input and sharing a
common data line (DSDA). The device enters the
Transmit-only mode upon power-up. In this mode, the
device transmits data bits on the DSDA pin in response
to a clock signal on the VCLK pin. The device will
remain in this mode until a valid high-to-low transition is
placed on the DSCL input. When a valid transition on
DSCL is recognized, the device will switch into the
Bidirectional mode and look for its control byte to be
sent by the master. If it detects its control byte, it will
stay in the Bidirectional mode. Otherwise, it will revert
to the Transmit-only mode after it sees 128 VCLK
pulses.
2.1.1
TRANSMIT-ONLY MODE
The device will power-up in the Transmit-only mode
at address 00H. This mode supports a unidirectional
2-wire protocol for transmission of the contents of the
memory array.
This device requires that it be initialized prior to valid
data being sent in the Transmit-only mode (see
Section 2.1.2 “Initialization Procedure”
). In this
mode, data is transmitted on the DSDA pin in 8-bit
bytes, each followed by a ninth, null bit (see Figure 2-
1). The clock source for the Transmit-only mode is
provided on the VCLK pin, and a data bit is output on
the rising edge on this pin. The eight bits in each byte
are transmitted by Most Significant bit first. Each byte
within the memory array will be output in sequence.
When the last byte in the memory array is transmit-
ted, the output will wrap around to the first location
and continue. The Bidirectional mode Clock (DSCL)
pin must be held high for the device to remain in the
Transmit-only mode.
2.1.2
After V
CC
has stabilized, the device will be in the
Transmit-only mode. Nine clock cycles on the VCLK pin
must be given to the device for it to perform internal
sychronization. During this period, the DSDA pin will be
in a high-impedance state. On the rising edge of the
tenth clock cycle, the device will output the first valid
data bit which will be the Most Significant bit of a byte.
The device will power-up at an indeterminate byte
address (Figure 2-2).
INITIALIZATION PROCEDURE
FIGURE 2-1:
TRANSMIT-ONLY MODE
FIGURE 2-2:
DEVICE INITIALIZATION
SCL
SDA
VCLK
T
VAA
T
VAA
Bit 1 (LSB)
Null Bit
Bit 1 (MSB)
Bit 7
T
VLOW
T
VHIGH
T
VAA
T
VAA
Bit 8
Bit 7
High-impedance for 9 clock cycles
T
VPU
1
2
8
9
10
11
SCL
SDA
VCLK
V
CC
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 24LC512/S16K | 制造商:Microchip Technology Inc 功能描述:512K, 64K X 8, 2.5V SER EE,IND - Gel-pak, waffle pack, wafer, diced wafer on film |
| 24LC512/W16K | 制造商:Microchip Technology Inc 功能描述:512K, 64K X 8, 2.5V SER EE,IND,WAFER - Gel-pak, waffle pack, wafer, diced wafer on film |
| 24LC512/WF16K | 制造商:Microchip Technology Inc 功能描述:512K, 64K X 8, 2.5V SER EE,IND - Gel-pak, waffle pack, wafer, diced wafer on film |
| 24LC512-E/MF | 功能描述:電可擦除可編程只讀存儲(chǔ)器 64kx8 - 2.5V RoHS:否 制造商:Atmel 存儲(chǔ)容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時(shí)鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| 24LC512-E/MS | 制造商:Microchip Technology Inc 功能描述:512K, 64K X 8, 2.5V SER EE, EXT - Rail/Tube 制造商:Microchip Technology Inc 功能描述:IC EEPROM 512KBIT 400KHZ 8MSOP 制造商:Microchip Technology Inc 功能描述:512K, 64K X 8, 2.5V SER EE, EXT, 8 MSOP 3x3mm TUBE |
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