參數(shù)資料
型號: 24LC41-IP
廠商: Microchip Technology Inc.
英文描述: 1K/4K 2.5V Dual Mode, Dual Port I 2 C Serial EEPROM
中文描述: 1K/4K 2.5V的雙模式,雙端口的I 2 C串行EEPROM
文件頁數(shù): 10/12頁
文件大?。?/td> 98K
代理商: 24LC41-IP
24LC41
DS21140B-page 10
1996 Microchip Technology Inc.
7.3
Sequential Read
Sequential reads are initiated in the same way as a ran-
dom read except that after the port transmits the first
data byte, and the master issues an acknowledge as
opposed to a stop condition in a random read. This
directs the port to transmit the next sequentially
addressed 8-bit word (Figure 7-3).
To provide sequential reads, the port contains an inter-
nal address pointer, which is incremented by one at the
completion of each operation. This address pointer
allows the entire memory contents to be serially read
during one operation.
7.4
Noise Protection
Both the DDC Monitor Port and Microcontroller Access
Port employ a V
CC
threshold detector circuit which dis-
ables the internal erase/write logic, if the V
CC
is below
1.5 volts at nominal conditions.
The DSCL, MSCL, DSDA, and MSDA inputs have
Schmitt trigger and filter circuits which suppress noise
spikes to assure proper device operation even on a
noisy bus.
FIGURE 7-1:
CURRENT ADDRESS READ
FIGURE 7-2:
RANDOM READ
FIGURE 7-3:
SEQUENTIAL READ
S
P
BUS ACTIVITY
MASTER
DSDA or
MSDA LINE
BUS ACTIVITY
S
T
A
R
T
CONTROL
BYTE
DATA n
A
C
K
N
O
A
C
K
S
T
O
P
S
P
S
BUS ACTIVITY
MASTER
MSDA LINE
BUS ACTIVITY
S
T
A
R
T
S
T
O
P
CONTROL
BYTE
WORD
ADDRESS (n)
DATA n
A
C
K
A
C
K
N
O
A
C
K
CONTROL
BYTE
A
C
K
S
T
A
R
T
P
DSDA or
MSDA LINE
BUS ACTIVITY
S
T
O
P
CONTROL
BYTE
DATA n
A
C
K
N
O
A
C
K
A
C
K
A
C
K
A
C
K
DATA n + 1
DATA n + 2
DATA n + X
BUS ACTIVITY
MASTER
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