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參數(shù)資料
| 型號： | 24LC21A |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | 1K 2.5V Dual Mode I 2 C Serial EEPROM |
| 中文描述： | 一千2.5V的雙模式的I 2 C串行EEPROM |
| 文件頁數(shù)： | 6/12頁 |
| 文件大小： | 81K |
| 代理商： | 24LC21A |
24LC21
DS21095F-page 6
1996 Microchip Technology Inc.
3.1.4
DATA VALID (D)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited, although only the last
eight will be stored when doing a write operation. When
an overwrite does occur it will replace data in a first in
first out fashion.
3.1.5
ACKNOWLEDGE
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
The device that acknowledges has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the last
byte that has been clocked out of the slave. In this
case, the slave must leave the data line HIGH to enable
the master to generate the STOP condition.
Note:
The 24LC21 does not generate any
acknowledge bits if an internal program-
ming cycle is in progress.
FIGURE 3-3:
BUS TIMING START/STOP
FIGURE 3-4:
BUS TIMING DATA
T
SU
:
STA
T
HD
:
STA
V
HYS
T
SU
:
STO
START
STOP
SCL
SDA
T
SU
:
STA
T
F
T
LOW
T
HIGH
T
R
T
HD
:
DAT
T
SU
:
DAT
T
SU
:
STO
T
HD
:
STA
T
BUF
T
AA
T
AA
T
SP
T
HD
:
STA
SCL
SDA
IN
SDA
OUT
相關PDF資料 |
PDF描述 |
|---|---|
| 24LC21A-IP | 1K 2.5V Dual Mode I 2 C Serial EEPROM |
| 24LC21A-ISN | 1K 2.5V Dual Mode I 2 C Serial EEPROM |
| 24LC21A-P | 1K 2.5V Dual Mode I 2 C Serial EEPROM |
| 24LC21A-SN | 1K 2.5V Dual Mode I 2 C Serial EEPROM |
| 24LC22A | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 24LC21A/P | 功能描述:電可擦除可編程只讀存儲器 2.5V Dual Mode RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| 24LC21A/SN | 功能描述:電可擦除可編程只讀存儲器 2.5V Dual Mode RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| 24LC21A/SN | 制造商:Microchip Technology Inc 功能描述:IC SM EEPROM SERIAL 1K |
| 24LC21A-I/P | 功能描述:電可擦除可編程只讀存儲器 2.5V Dual Mode RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| 24LC21A-I/PG | 功能描述:電可擦除可編程只讀存儲器 2.5V Dual Mode Lead Free Package RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-8 |
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