參數(shù)資料
型號: 24LC21A-ISN
廠商: Microchip Technology Inc.
英文描述: 1K 2.5V Dual Mode I 2 C Serial EEPROM
中文描述: 一千2.5V的雙模式的I 2 C串行EEPROM
文件頁數(shù): 5/12頁
文件大?。?/td> 81K
代理商: 24LC21A-ISN
1996 Microchip Technology Inc.
DS21095F-page 5
24LC21
3.0
BI-DIRECTIONAL MODE
The 24LC21 can be switched into the Bi-Directional
Mode (see Figure 3-1) by applying a valid high to low
transition on the Bi-Directional Mode Clock (SCL).
When the device has been switched into the Bi-Direc-
tional Mode, the VCLK input is disregarded, with the
exception that a logic high level is required to enable
write capability. This mode supports a two wire bi-direc-
tional data transmission protocol. In this protocol, a
device that sends data on the bus is defined to be the
transmitter, and a device that receives data from the
bus is defined to be the receiver. The bus must be con-
trolled by a master device that generates the Bi-Direc-
tional Mode Clock (SCL), controls access to the bus
and generates the START and STOP conditions, while
the 24LC21 acts as the slave. Both master and slave
can operate as transmitter or receiver, but the master
device determines which mode is activated.
3.1
Bi-Directional Mode Bus
Characteristics
The following
bus protocol
has been defined:
Data transfer may be initiated only when the bus is
not busy.
During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
Accordingly, the following bus conditions have been
defined (see Figure 3-2).
3.1.1
BUS NOT BUSY (A)
Both data and clock lines remain HIGH.
3.1.2
START DATA TRANSFER (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.
3.1.3
STOP DATA TRANSFER (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
FIGURE 3-1:
MODE TRANSITION
FIGURE 3-2:
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
SCL
SDA
VCLK
Bi-Directional Mode
T
VHZ
Transmit Only Mode
T
SU
:
STA
T
HD
:
STA
V
HYS
T
SU
:
STO
START
STOP
SCL
SDA
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