參數(shù)資料
型號: 24LC21-ISN
廠商: Microchip Technology Inc.
英文描述: 1K 2.5V Dual Mode I 2 C Serial EEPROM
中文描述: 一千2.5V的雙模式的I 2 C串行EEPROM
文件頁數(shù): 4/12頁
文件大小: 81K
代理商: 24LC21-ISN
24LC21
DS21095F-page 4
1996 Microchip Technology Inc.
2.0
FUNCTIONAL DESCRIPTION
The 24LC21 operates in two modes, the Transmit-Only
Mode and the Bi-Directional Mode. There is a separate
two wire protocol to support each mode, each having a
separate clock input and sharing a common data line
(SDA). The device enters the Transmit-Only Mode upon
power-up. In this mode, the device transmits data bits
on the SDA pin in response to a clock signal on the
VCLK pin. The device will remain in this mode until a
valid high to low transition is placed on the SCL input.
When a valid transition on SCL is recognized, the
device will switch into the Bi-Directional Mode. The only
way to switch the device back to the Transmit-Only
Mode is to remove power from the device.
2.1
Transmit-Only Mode
The device will power up in the Transmit-Only Mode.
This mode supports a unidirectional two wire protocol
for transmission of the contents of the memory array.
This device requires that it be initialized prior to valid
data being sent in the Transmit-Only Mode (see Initial-
ization Procedure, below). In this mode, data is trans-
mitted on the SDA pin in 8 bit bytes, each followed by a
ninth, null bit (see Figure 2-1). The clock source for the
Transmit-Only Mode is provided on the VCLK pin, and
a data bit is output on the rising edge on this pin. The
eight bits in each byte are transmitted most significant
bit first. Each byte within the memory array will be out-
put in sequence. When the last byte in the memory
array is transmitted, the output will wrap around to the
first location and continue. The Bi-Directional Mode
Clock (SCL) pin must be held high for the device to
remain in the Transmit-Only Mode.
2.2
Initialization Procedure
After V
mit-Only Mode. Nine clock cycles on the VCLK pin must
be given to the device for it to perform internal synchro-
nization. During this period, the SDA pin will be in a high
impedance state. On the rising edge of the tenth clock
cycle, the device will output the first valid data bit which
will be the most significant bit of a byte. The device will
power up at an indeterminate byte address. (See
Figure 2-2).
CC
has stabilized, the device will be in the Trans-
FIGURE 2-1:
TRANSMIT ONLY MODE
FIGURE 2-2:
DEVICE INITIALIZATION
SCL
SDA
VCLK
T
VAA
T
VAA
B
IT
1 (LSB)
N
ULL
B
IT
B
IT
1 (MSB)
B
IT
7
T
VLOW
T
VHIGH
T
VAA
T
VAA
B
IT
8
B
IT
7
H
IGH
I
MPEDANCE
FOR
9
CLOCK
CYCLES
T
VPU
1
2
8
9
10
11
SCL
SDA
VCLK
V
CC
相關(guān)PDF資料
PDF描述
24LC21 1K 2.5V Dual Mode I 2 C Serial EEPROM
24LC21-P Connector; Leaded Process Compatible:Yes; Peak Reflow Compatible (260 C):Yes
24LC21-SN 1K 2.5V Dual Mode I 2 C Serial EEPROM
24LC21A 1K 2.5V Dual Mode I 2 C Serial EEPROM
24LC21A-IP 1K 2.5V Dual Mode I 2 C Serial EEPROM
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