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參數(shù)資料
| 型號： | 24LC040-EP |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | 4K SPI ⑩ Bus Serial EEPROM |
| 中文描述： | ⑩4K的的SPI總線串行EEPROM |
| 文件頁數(shù)： | 9/12頁 |
| 文件大?。?/td> | 240K |
| 代理商： | 24LC040-EP |
25AA040/25LC040/25C040
1997 Microchip Technology Inc.
Preliminary
DS21204A-page 9
3.5
Read Status Register (RDSR)
The RDSR instruction provides access to the status
register. The status register may be read at any time,
even during a write cycle. The status register is format-
ted as follows:
The
Write-In-Process (WIP)
bit indicates whether the
25xx040 is busy with a write operation. When set to a
‘1’ a write is in progress, when set to a ‘0’ no write is in
progress. This bit is read only.
The
Write Enable Latch (WEL)
bit indicates the status
of the write enable latch. When set to a ‘1’ the latch
allows writes to the array, when set to a ‘0’ the latch
prohibits writes to the array. The state of this bit can
always be updated via the WREN or WRDI commands
regardless of the state of write protection on the status
register. This bit is read only.
The
Block Protection (BP0 and BP1)
bits indicate
which blocks are currently write protected. These bits
are set by the user issuing the WRSR instruction.
These bits are non-volatile.
See Figure 3-6 for RDSR timing sequence
3.6
Write Status Register(WRSR)
The WRSR instruction allows the user to select one of
four levels of protection for the array by writing to the
appropriate bits in the status register. The array is
divided up into four segments. The user has the ability
to write protect none, one, two, or all four of the seg-
ments of the array. The partitioning is controlled as
illustrated in Table 3-2.
See Figure 3-7 for WRSR timing sequence
TABLE 3-2:
ARRAY PROTECTION
FIGURE 3-6:
READ STATUS REGISTER SEQUENCE
FIGURE 3-7:
WRITE STATUS REGISTER SEQUENCE
7
X
6
X
5
X
4
X
3
2
1
0
BP1
BP0
WEL
WIP
BP1
BP0
Array Addresses
Write Protected
0
0
none
upper 1/4
(0180h - 01FFh)
upper 1/2
(0100h - 01FFh)
all
(0000h - 01FFh)
0
1
1
0
1
1
SO
SI
CS
9
10
11
12
13
14
15
1
1
0
0
0
0
0
0
7
6
5
4
2
1
0
instruction
data from status register
high impedance
SCK
0
2
3
4
5
6
7
1
8
3
SO
SI
CS
9
10
11
12
13
14
15
0
1
0
0
0
0
0
0
7
6
5
4
2
1
0
instruction
data to status register
high impedance
SCK
0
2
3
4
5
6
7
1
8
3
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相關代理商/技術參數(shù) |
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| 24LC040-ESN | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:4K SPI ⑩ Bus Serial EEPROM |
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| 24LC040-ISN | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:4K SPI ⑩ Bus Serial EEPROM |
| 24LC040-IST | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:4K SPI ⑩ Bus Serial EEPROM |
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