參數(shù)資料
型號: 24LC025SN
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù): 3/12頁
文件大小: 182K
代理商: 24LC025SN
24LC024/24LC025
1999 Microchip Technology Inc.
DS21210D-page 3
TABLE 1-3:
AC CHARACTERISTICS
FIGURE 1-1:
BUS TIMING DATA
All parameters apply across the specified operat-
ing ranges unless otherwise noted.
Vcc = 2.2V to 5.5V
Commercial (C):
Industrial (I):
Tamb = 0°C to +70°C
Tamb = -40°C to +85°C
Parameter
Symbol
Vcc = 2.2V - 5.5V
STD MODE
Vcc = 4.5V - 5.5V
FAST MODE
Units
Remarks
Min.
4000
4700
4000
Max.
100
1000
300
Min.
600
1300
600
Max.
400
300
300
Clock frequency
Clock high time
Clock low time
SDA and SCL rise time
SDA and SCL fall time
START condition hold time
F
CLK
T
HIGH
T
LOW
T
R
T
F
T
HD
:
STA
kHz
ns
ns
ns
ns
ns
(Note 1)
(Note 1)
After this period the first
clock pulse is generated
Only relevant for repeated
START condition
(Note 2)
START condition setup time
T
SU
:
STA
4700
600
ns
Data input hold time
Data input setup time
STOP condition setup time
Output valid from clock
Bus free time
T
HD
:
DAT
T
SU
:
DAT
T
SU
:
STO
T
AA
T
BUF
0
0
900
ns
ns
ns
ns
ns
250
4000
4700
100
600
1300
3500
(Note 2)
Time the bus must be free
before a new transmission
can start
(Note 1), C
B
100 pF
Output fall time from V
IH
minimum to V
IL
maximum
Input filter spike suppression
(SDA and SCL pins)
Write cycle time
Endurance
T
OF
250
20 +0.1
C
B
250
ns
T
SP
50
50
ns
(Note 3)
T
WC
1M
10
1M
10
ms
Byte or Page mode
cycles 25°C, V
CC
= 5.0V, Block
Mode (Note 4)
Note 1:
Not 100% tested. C
B
= total capacitance of one bus line in pF.
2:
As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3:
The combined T
SP
and V
HYS
specifications are due to Schmitt trigger inputs which provide improved noise
spike suppression. This eliminates the need for a TI specification for standard operation.
4:
This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific
application, please consult the Total Endurance Model which can be obtained on our website.
SCL
SDA
IN
T
SU
:
STA
SDA
OUT
T
HD
:
STA
T
LOW
T
HIGH
T
R
T
BUF
T
AA
T
HD
:
DAT
T
SU
:
DAT
T
SU
:
STO
T
SP
T
F
This Material Copyrighted by Its Respective Manufacturer
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