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參數(shù)資料
| 型號(hào)： | 24LC014T-I/MSG |
| 元件分類(lèi)： | PROM |
| 英文描述： | 128 X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8 |
| 封裝： | LEAD FREE, PLASTIC, MO-187, MSOP-8 |
| 文件頁(yè)數(shù)： | 9/9頁(yè) |
| 文件大?。?/td> | 876K |
| 代理商： | 24LC014T-I/MSG |
2005 Microchip Technology Inc.
DS21930A-page 9
24AAXX/24LCXX/24FCXX
3.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
PIN FUNCTION TABLE
3.1
A0, A1, A2 Chip Address Inputs
The A0, A1 and A2 pins are not used by the 24XX01
through 24XX16 devices.
The A0, A1 and A2 inputs are used by the 24C01C,
24C02C, 24XX014, 24XX024, 24XX025 and the
24XX32 through 24XX512 for multiple device opera-
tions. The levels on these inputs are compared with the
corresponding bits in the slave address. The chip is
selected if the compare is true.
For the 24XX128 and 24XX256 in the MSOP package
only, pins A0 and A1 are not connected.
Up to eight devices (two for the 24XX128 and
24XX256 MSOP package) may be connected to the
same
bus
by
using
different
Chip
Select
bit
combinations.
In most applications, the chip address inputs A0, A1
and A2 are hard-wired to logic ‘0’ or logic ‘1’. For
applications in which these pins are controlled by a
microcontroller or other programmable device, the chip
address pins must be driven to logic ‘0’ or logic ‘1’
before normal device operation can proceed.
3.2
Serial Data (SDA)
This is a bidirectional pin used to transfer addresses
and data into and out of the device. It is an open drain
terminal. Therefore, the SDA bus requires a pull-up
resistor to V
CC (typical 10 k
Ω for 100kHz, 2kΩ for
400 kHz and 1 MHz).
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
3.3
Serial Clock (SCL)
This input is used to synchronize the data transfer to
and from the device.
3.4
Write-Protect (WP)
This pin must be connected to either V
SS or VCC. If tied
to V
SS, write operations are enabled. If tied to VCC,
write operations are inhibited but read operations are
not affected. See Table 1-1 for the write-protect
scheme of each device.
3.5
Power Supply (V
CC)
A V
CC threshold detect circuit is employed which
disables the internal erase/write logic if V
CC is below
1.5V at nominal conditions. For the 24C00, 24C01C
and 24C02C devices, the erase/write logic is disabled
below 3.8V at nominal conditions.
Pin
Name
8-Pin
PDIP and
SOIC
8-Pin
TSSOP and
MSOP
5-Pin SOT-23
24XX00
5-Pin SOT-23
All except
24XX00
14-Pin
TSSOP
8-Pin
5x6 DFN and
2x3 DFN
Function
A0
1
1(1)
—
1
User configurable Chip Select(3)
A1
2
2(1)
——
2
User configurable Chip Select(3)
A2
3
—
6
3
User configurable Chip Select(3)
V
SS
4
2
7
4
Ground
SDA
5
3
8
5
Serial Data
SCL
6
1
9
6
Serial Clock
(NC)
—
4
—
3, 4, 5,
10, 11, 12
—
Not Connected
WP
7(2)
—
5
13
7
Write-Protect Input
V
CC
8
5
4
14
8
Power Supply
Note
1:
Pins 1 and 2 are not connected for the 24XX128 and 24XX256 MSOP packages.
2:
Pin 7 is not used for 24XX00, 24XX025 and 24C01C.
3:
Pins A0, A1 and A2 are not used by some devices (no internal connections). See Table 1-1 for details.
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