參數(shù)資料
型號(hào)： 24C64
廠商： SIEMENS AG
英文描述： 64 Kbit 8192 x 8 bit Serial CMOS EEPROMs, I2C Synchronous 2-Wire Bus
中文描述： 64千位8192 × 8位串行CMOS EEPROM的，I2C同步2線總線
文件頁(yè)數(shù)： 8/12頁(yè)
文件大?。?/td> 84K
代理商： 24C64
CAT24C323/643
8
Advanced
Doc. No. 25084-00 12/98
Figure 7. Byte Write Timing
Figure 8. Page Write Timing
ACKNOWLEDGE
After a successful data transfer, each receiving device is
required to generate an acknowledge. The Acknowledg-
ing device pulls down the SDA line during the ninth clock
cycle, signaling that it received the 8 bits of data.
The CAT24CXXX responds with an acknowledge after
receiving a START condition and its slave address. If the
device has been selected along with a write operation,
it responds with an acknowledge after receiving each 8-
bit byte.
When the CAT24CXXX begins a READ mode it trans-
mits 8 bits of data, releases the SDA line, and monitors
the line for an acknowledge. Once it receives this ac-
knowledge, the CAT24CXXX will continue to transmit
data. If no acknowledge is sent by the Master, the device
terminates data transmission and waits for a STOP
condition.
WRITE OPERATIONS
Byte Write
In the Byte Write mode, the Master device sends the
START condition and the slave address information
(with the R/
W
bit set to zero) to the Slave device. After
t he Slave generates an acknowledge, the Master sends
a 8-bit address that is to be written into the address
pointers of the CAT24CXXX. After receiving another
acknowledge from the Slave, the Master device trans-
mits the data to be written into the addressed memory
location. The CAT24CXXX acknowledges once more
and the Master generates the STOP condition. At this
time, the device begins an internal programming cycle to
nonvolatile memory. While the cycle is in progress, the
device will not respond to any request from the Master
device.
Page Write
The 24CXXX writes up to 32 bytes of data in a single
write cycle, using the Page Write operation. The page
write operation is initiated in the same manner as the
byte write operation, however instead of terminating
after the initial byte is transmitted, the Master is allowed
to send up to 31 additional bytes. After each byte has
been transmitted, CAT24CXXX will respond with an
acknowledge, and internally increment the lower order
address bits by one. The high order bits remain un-
changed.
If the Master transmits more than 32 bytes before
sending the STOP condition, the address counter ‘wraps
around’, and previously transmitted data will be overwrit-
ten.
When all 32 bytes are received, and the STOP condi
tion has been sent by the Master, the internal program-
ming cycle begins. At this point, all received data is
written to the CAT24CXXX in a single write cycle.
* = Don't care bit for 24C323
X= Don't care bit
A15–A8
SLAVE
ADDRESS
S
A
C
K
A
C
K
DATA
A
C
K
S
T
O
P
P
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
A7–A0
BYTE ADDRESS
A
C
K
*
X
X X
A15–A8
SLAVE
ADDRESS
S
A
C
K
A
C
K
A
C
K
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
A7–A0
BYTE ADDRESS
DATA n+31
DAT
A
C
K
S
T
O
P
A
C
K
DATA
A
C
K
P
A
C
K
*
X
X X
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