- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄368878 > 24C32ATISN I2C Serial EEPROM PDF資料下載
參數(shù)資料
| 型號： | 24C32ATISN |
| 英文描述： | I2C Serial EEPROM |
| 中文描述： | I2C串行EEPROM的 |
| 文件頁數(shù)： | 4/12頁 |
| 文件大?。?/td> | 177K |
| 代理商： | 24C32ATISN |
24C32A
DS21163D-page 4
1999 Microchip Technology Inc.
2.0
FUNCTIONAL DESCRIPTION
The 24C32A supports a Bi-directional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, and a device
receiving data as receiver. The bus must be controlled
by a master device which generates the Serial Clock
(SCL), controls the bus access, and generates the
START and STOP conditions, while the 24C32A works
as slave. Both master and slave can operate as trans-
mitter or receiver but the master device determines
which mode is activated.
3.0
BUS CHARACTERISTICS
The following
bus protocol
has been defined:
Data transfer may be initiated only when the bus
is not busy.
During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
Accordingly, the following bus conditions have been
defined (Figure 3-1).
3.1
Bus not Busy (A)
Both data and clock lines remain HIGH.
3.2
Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.
3.3
Stop Data Transfer (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
3.4
Data Valid (D)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device.
3.5
Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge signal after the reception of
each byte. The master device must generate an extra
clock pulse which is associated with this acknowledge
bit.
A device that acknowledges must pull down the SDA
line during the acknowledge clock pulse in such a way
that the SDA line is stable LOW during the HIGH period
of the acknowledge related clock pulse. Of course,
setup and hold times must be taken into account. Dur-
ing reads, a master must signal an end of data to the
slave by NOT generating an acknowledge bit on the last
byte that has been clocked out of the slave. In this case,
the slave (24C32A) will leave the data line HIGH to
enable the master to generate the STOP condition.
Note:
The 24C32A does not generate any
acknowledge bits if an internal program-
ming cycle is in progress.
FIGURE 3-1:
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
SCL
SDA
(A)
(B)
(D)
(D)
(C)
(A)
START
CONDITION
ADDRESS OR
ACKNOWLEDGE
VALID
DATA
ALLOWED
TO CHANGE
STOP
CONDITION
This Material Copyrighted by Its Respective Manufacturer
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 24C32ATSM | I2C Serial EEPROM |
| 24C32ATSN | I2C Serial EEPROM |
| 24C32 | 32K 5.0V I2C Smart Serial EEPROM |
| 24C64 | DIODE ZENER 15.0V 150MW SSMINI2 |
| 24C64 | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 24C32ATSM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:I2C Serial EEPROM |
| 24C32ATSN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:I2C Serial EEPROM |
| 24C32I/P | 制造商:Microchip Technology 功能描述:EEPROM Serial 32K-bit 4K x 8 5V 8-Pin PDIP |
| 24C32-I/P | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:32K 5.0V I2C Smart Serial EEPROM |
| 24C32I/SM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:I2C Serial EEPROM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。