- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄368878 > 24C32AP I2C Serial EEPROM PDF資料下載
參數(shù)資料
| 型號： | 24C32AP |
| 英文描述： | I2C Serial EEPROM |
| 中文描述： | I2C串行EEPROM的 |
| 文件頁數(shù)： | 9/12頁 |
| 文件大?。?/td> | 177K |
| 代理商： | 24C32AP |
1999 Microchip Technology Inc.
DS21163D-page 9
24C32A
7.0
PIN DESCRIPTIONS
7.1
A0, A1, A2 Chip Address Inputs
The A0..A2 inputs are used by the 24C32A for multiple
device operation and conform to the 2-wire bus stan-
dard. The levels applied to these pins define the
address block occupied by the device in the address
map. A particular device is selected by transmitting the
corresponding bits (A2, A1, A0) in the control byte
(Figure 3-3).
7.2
SDA Serial Address/Data Input/Output
This is a Bi-directional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal, therefore the SDA bus requires a pullup
resistor to V
CC
(typical 10K
for 100 kHz, 2 K
for
400 kHz)
For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL HIGH are
reserved for indicating the START and STOP condi-
tions.
7.3
SCL Serial Clock
This input is used to synchronize the data transfer from
and to the device.
7.4
WP
This pin must be connected to either V
SS
or V
CC
.
If tied to V
SS
, normal memory operation is enabled
(read/write the entire memory 000-FFF).
If tied to V
CC
, WRITE operations are inhibited. The
entire memory will be write-protected. Read operations
are not affected.
8.0
NOISE PROTECTION
The SCL and SDA inputs have filter circuits which sup-
press noise spikes to ensure proper device operation
even on a noisy bus. All I/O lines incorporate Schmitt
triggers for 400 kHz (Fast Mode) compatibility.
9.0
POWER MANAGEMENT
This design incorporates a power standby mode when
the device is not in use and automatically powers off
after the normal termination of any operation when a
stop bit is received and all internal functions are com-
plete. This includes any error conditions, i.e., not
receiving an acknowledge or stop condition per the
two-wire bus specification. The device also incorpo-
rates V
DD
monitor circuitry to prevent inadvertent writes
(data corruption) during low-voltage conditions. The
V
DD
monitor circuitry is powered off when the device is
in standby mode in order to further reduce power con-
sumption.
This Material Copyrighted by Its Respective Manufacturer
相關PDF資料 |
PDF描述 |
|---|---|
| 24C32ASM | I2C Serial EEPROM |
| 24C32ASN | I2C Serial EEPROM |
| 24C32ATESM | I2C Serial EEPROM |
| 24C32ATESN | I2C Serial EEPROM |
| 24C32ATISM | Silicon Serial Number |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 24C32A-P | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:32K 5.0V I 2 C O Serial EEPROM |
| 24C32ASM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:I2C Serial EEPROM |
| 24C32A-SM | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:32K 5.0V I 2 C O Serial EEPROM |
| 24C32ASN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:I2C Serial EEPROM |
| 24C32A-SN | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:32K 5.0V I 2 C O Serial EEPROM |
發(fā)布緊急采購，3分鐘左右您將得到回復。