1996 Microchip Technology Inc.
Preliminary
DS21163B-page 3
24C32A
TABLE 1-3:
AC CHARACTERISTICS
FIGURE 1-2:
BUS TIMING DATA
Parameter
Symbol
Vcc = 4.5-5.5
Units
Remarks
Min
Max
Clock frequency
Clock high time
Clock low time
SDA and SCL rise time
SDA and SCL fall time
START condition hold time
F
T
T
CLK
—
100
—
—
1000
300
—
kHz
ns
ns
ns
ns
ns
HIGH
4000
4700
—
—
4000
LOW
T
R
T
F
:
STA
(Note 1)
(Note 1)
After this period the first clock
pulse is generated
Only relevant for repeated
START condition
T
HD
START condition setup time
T
SU
:
STA
4700
—
ns
Data input hold time
Data input setup time
STOP condition setup time
Output valid from clock
Bus free time
T
T
T
HD
:
:
:
DAT
0
—
—
—
ns
ns
ns
ns
ns
SU
DAT
250
4000
—
4700
SU
T
T
STO
AA
3500
—
(Note 2)
Time the bus must be free before
a new transmission can start
(Note 1), C
B
≤
100 pF
BUF
Output fall time from V
V
IL
max
Input filter spike suppression
(SDA and SCL pins)
Write cycle time
Endurance
IH
min to
T
OF
—
250
ns
T
SP
—
50
ns
(Note 3)
T
WR
—
—
1M
5
—
ms
cycles
25
(Note 4)
°
C, Vcc = 5.0V, Block Mode
Note 1: Not 100% tested. C
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined T
SP
and V
HYS
specifications are due to Schmitt trigger inputs which provide improved noise
and spike suppression. This eliminates the need for a Ti specification for standard operation.
4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-
cation, please consult the Total Endurance Model which can be obtained on our BBS or website.
B
= Total capacitance of one bus line in pF.
SCL
SDA
IN
SDA
OUT
T
HD
:
STA
T
SU
:
STA
T
F
T
HIGH
T
R
T
SU
:
STO
T
SU
:
DAT
T
HD
:
DAT
T
BUF
T
AA
T
HD
:
STA
T
AA
T
SP
T
LOW