1996 Microchip Technology Inc.
DS21081D-page 3
24C08B/16B
TABLE 1-3:
AC CHARACTERISTICS
FIGURE 1-2:
BUS TIMING DATA
Parameter
Symbol
F
CLK
T
HIGH
T
LOW
T
R
T
T
HD
:
Min
—
4000
4700
—
—
4000
Max
100
—
—
1000
300
—
Units
kHz
ns
ns
ns
ns
ns
Remarks
Clock frequency
Clock high time
Clock low time
SDA and SCL rise time
SDA and SCL fall time
START condition hold time
(Note1)
(Note 1)
After this period the first clock
pulse is generated
Only relevant for repeated
START condition
F
STA
START condition setup time
T
SU
:
STA
4700
—
ns
Data input hold time
Data input setup time
STOP condition setup time
Output valid from clock
Bus free time
T
T
T
HD
:
:
:
DAT
0
—
—
—
ns
ns
ns
ns
ns
SU
DAT
250
4000
—
4700
SU
T
T
STO
AA
3500
—
(Note 2)
Time the bus must be free before
a new transmission can start
(Note 1), C
B
≤
100 pF
BUF
Output fall time from V
min to V
IL
max
Input filter spike suppres-
sion (SDA and SCL pins)
Write cycle time
Endurance
IH
T
OF
—
250
ns
T
SP
—
50
ns
(Note 3)
T
WR
—
—
—
1M
10M
10
—
—
ms
Byte or Page mode
25
°
C, V
CC
(Note 4)
24C08B
24C16B
cycles
= 5.0V, Block Mode
Note 1: Not 100% tested. C
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined T
SP
and V
HYS
specifications are due to new Schmitt trigger inputs which provide improved
noise and spike suppression. This eliminates the need for a T
4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-
cation, please consult the Total Endurance Model which can be obtained on our BBS or website.
B
= total capacitance of one bus line in pF.
I
specification.
T
SU
:
STA
T
F
T
LOW
T
HIGH
T
R
T
HD
:
DAT
T
SU
:
DAT
T
SU
:
STO
T
HD
:
STA
T
BUF
T
AA
T
AA
T
SP
T
HD
:
STA
SCL
SDA
IN
SDA
OUT