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| 型號(hào)： | 24C16B-ESL |
| 廠商： | Microchip Technology Inc. |
| 元件分類： | EEPROM |
| 英文描述： | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| 中文描述： | 該CAT24FC02是一個(gè)2 KB的EEPROM的國(guó)內(nèi)256個(gè)8位每字舉辦的串行CMOS |
| 文件頁(yè)數(shù)： | 5/12頁(yè) |
| 文件大?。?/td> | 75K |
| 代理商： | 24C16B-ESL |
1996 Microchip Technology Inc.
DS21081D-page 5
24C08B/16B
3.6
Device Addressing
A control byte is the first byte received following the
start condition from the master device. The control byte
consists of a 4-bit control code, for the 24C08B/16B this
is set as 1010 binary for read and write operations. The
next three bits of the control byte are the block select
bits (B2, B1, B0). They are used by the master device
to select which of the eight 256 word blocks of memory
are to be accessed. These bits are in effect the three
most significant bits of the word address.
The last bit of the control byte defines the operation to
be performed. When set to one a read operation is
selected, when set to zero a write operation is selected.
Following the start condition, the 24C08B/16B monitors
the SDA bus checking the device type identifier being
transmitted, upon a 1010 code the slave device outputs
an acknowledge signal on the SDA line. Depending on
the state of the R/W bit, the 24C08B/16B will select a
read or write operation.
FIGURE 3-2:
CONTROL BYTE
ALLOCATION
Operation
Control
Code
1010
1010
Block Select
R/W
Read
Write
Block Address
Block Address
1
0
SLAVE ADDRESS
1
0
1
0
B2
B1
B0
R/W
A
START
READ/WRITE
4.0
WRITE OPERATION
4.1
Byte Write
Following the start condition from the master, the
device code (4 bits), the block address (3 bits), and the
R/W bit which is a logic low is placed onto the bus by
the master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will follow
after it has generated an acknowledge bit during the
ninth clock cycle. Therefore the next byte transmitted by
the master is the word address and will be written into
the address pointer of the 24C08B/16B. After receiving
another acknowledge signal from the 24C08B/16B the
master device will transmit the data word to be written
into the addressed memory location. The 24C08B/16B
acknowledges again and the master generates a stop
condition. This initiates the internal write cycle, and dur-
ing this time the 24C08B/16B will not generate
acknowledge signals (Figure 4-1).
4.2
Page Write
The write control byte, word address and the first data
byte are transmitted to the 24C08B/16B in the same
way as in a byte write. But instead of generating a stop
condition the master transmits up to 16 data bytes to
the 24C08B/16B which are temporarily stored in the on-
chip page buffer and will be written into the memory
after the master has transmitted a stop condition. After
the receipt of each word, the four lower order address
pointer bits are internally incremented by one. The
higher order seven bits of the word address remains
constant. If the master should transmit more than 16
words prior to generating the stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the stop condition is received an inter-
nal write cycle will begin (Figure 4-2).
FIGURE 4-1:
BYTE WRITE
S
T
A
R
T
FIGURE 4-2:
PAGE WRITE
T
A
R
T
S
P
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
O
P
CONTROL
BYTE
WORD
ADDRESS
DATA
A
C
K
A
C
K
A
C
K
S
P
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
CONTROL
BYTE
WORD
ADDRESS (n)
DATA n
DATA n + 15
S
T
O
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
DATA n + 1
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