24C08B/16B
DS21081C-page 6
1995 Microchip Technology Inc.
6.0
ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the stop condition for a write com-
mand has been issued from the master, the device ini-
tiates the internally timed write cycle. ACK polling can
be initiated immediately. This involves the master
sending a start condition followed by the control byte
for a write command (R/W = 0). If the device is still
busy with the write cycle, then no ACK will be returned.
If the cycle is complete, then the device will return the
ACK and the master can then proceed with the next
read or write command. See Figure 6-1 for flow dia-
gram.
FIGURE 6-1:
ACKNOWLEDGE POLLING
FLOW
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
Acknowledge
(ACK = 0)
Next
Operation
No
Yes
7.0
WRITE PROTECTION
The 24C08B/16B can be used as a serial ROM when
the WP pin is connected to V
inhibited and the entire memory will be write-protected.
8.0
READ OPERATION
CC
. Programming will be
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
slave address is set to one. There are three basic
types of read operations: current address read, ran-
dom read, and sequential read.
8.1
Current Address Read
The 24C08B/16B contains an address counter that
maintains the address of the last word accessed, inter-
nally incremented by one. Therefore, if the previous
access (either a read or write operation) was to
address n, the next current address read operation
would access data from address n + 1. Upon receipt of
the slave address with R/W bit set to one, the 24C08B/
16B issues an acknowledge and transmits the eight bit
data word. The master will not acknowledge the trans-
fer but does generate a stop condition and the 24C08B/
16B discontinues transmission (see Figure 8-2).
8.2
Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
24C08B/16B as part of a write operation. After the
word address is sent, the master generates a start con-
dition following the acknowledge. This terminates the
write operation, but not before the internal address
pointer is set. Then the master issues the control byte
again but with the R/W bit set to a one. The 24C08B/
16B will then issue an acknowledge and transmits the
eight bit data word. The master will not acknowledge
the transfer but does generate a stop condition and the
24C08B/16B discontinues transmission (see Figure 8-
3).
FIGURE 8-1:
PAGE WRITE
S
T
O
P
SDA LINE
P
DATA n
S
T
A
R
T
CONTROL
BYTE
S
WORD
ADDRESS (n)
BUS ACTIVITY:
MASTER
BUS ACTIVITY:
A
C
K
A
C
K
A
C
K
DATA n + 1
A
C
K
DATA n + 15
A
C
K