參數(shù)資料
型號(hào): 24C02SCWF08
英文描述: I2C Serial EEPROM
中文描述: I2C串行EEPROM的
文件頁(yè)數(shù): 8/12頁(yè)
文件大小: 168K
代理商: 24C02SCWF08
24C01SC/02SC
DS21170D-page 8
1999 Microchip Technology Inc.
6.3
Sequential Read
Sequential reads are initiated in the same way as a ran-
dom read except that after the 24C01SC/02SC trans-
mits the first data byte, the master issues an
acknowledge as opposed to a stop condition in a ran-
dom read. This directs the 24C01SC/02SC to transmit
the
next
sequentially
(Figure 6-3).
To provide sequential reads the 24C01SC/02SC con-
tains an internal address pointer which is incremented
by one at the completion of each operation. This
address pointer allows the entire memory contents to
be serially read during one operation.
addressed
8-bit
word
6.4
Noise Protection
The 24C01SC/02SC employs a V
CC
threshold detector
circuit which disables the internal erase/write logic if the
V
CC
is below 1.5 volts at nominal conditions.
The SCL and SDA inputs have Schmitt trigger and filter
circuits which suppress noise spikes to assure proper
device operation even on a noisy bus.
FIGURE 6-1:
CURRENT ADDRESS READ
FIGURE 6-2:
RANDOM READ
FIGURE 6-3:
SEQUENTIAL READ
S
P
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
A
R
T
CONTROL
BYTE
DATA n
A
C
K
N
O
A
C
K
S
T
O
P
S
P
S
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
A
R
T
S
T
O
P
CONTROL
BYTE
WORD
ADDRESS (n)
DATA n
A
C
K
A
C
K
N
O
A
C
K
CONTROL
BYTE
A
C
K
S
T
A
R
T
P
SDA LINE
BUS ACTIVITY
S
T
O
P
CONTROL
BYTE
DATA n
A
C
K
N
O
A
C
K
A
C
K
A
C
K
A
C
K
DATA n + 1
DATA n + 2
DATA n + X
BUS ACTIVITY
MASTER
This Material Copyrighted by Its Respective Manufacturer
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