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參數(shù)資料
| 型號： | 24C02SC-WF |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | 24C01C-P 24C01C-IP 24C01C-EP 24C01C-SN 24C01C-ISN 24C01C-ESN 24C01C-ST 24C01C-IST 24C01C-EST |
| 中文描述： | 24C01C磷24C01C的IP 24C01C -內啡肽24C01C錫24C01C，無法真正傳達24C01C - ESN的24C01C ST段24C01C -北京時間24C01C -學報 |
| 文件頁數(shù)： | 4/12頁 |
| 文件大?。?/td> | 174K |
| 代理商： | 24C02SC-WF |
24C02C
DS21202C-page 4
1999 Microchip Technology Inc.
2.0
PIN DESCRIPTIONS
2.1
SDA Serial Data
This is a bi-directional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal, therefore the SDA bus requires a pull-up
resistor to V
CC
(typical 10 k
for 100 kHz, 2 k
for
400 kHz).
For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the START and STOP condi-
tions.
2.2
SCL Serial Clock
This input is used to synchronize the data transfer from
and to the device.
2.3
A0, A1, A2
The levels on these inputs are compared with the cor-
responding bits in the slave address. The chip is
selected if the compare is true.
Up to eight 24C02C devices may be connected to the
same bus by using different chip select bit combina-
tions. These inputs must be connected to either V
CC
or
V
SS
.
2.4
WP
This is the hardware write protect pin. It must be tied to
V
CC
or V
SS
. If tied to Vcc, the hardware write protection
is enabled. If the WP pin is tied to Vss the hardware
write protection is disabled.
2.5
Noise Protection
The 24C02C employs a V
CC
threshold detector circuit
which disables the internal erase/write logic if the V
CC
is below 3.8 volts at nominal conditions.
The SCL and SDA inputs have Schmitt trigger and filter
circuits which suppress noise spikes to assure proper
device operation even on a noisy bus.
3.0
FUNCTIONAL DESCRIPTION
The 24C02C supports a bi-directional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, and a device
receiving data as receiver. The bus has to be controlled
by a master device which generates the serial clock
(SCL), controls the bus access, and generates the
START and STOP conditions, while the 24C02C works
as slave. Both master and slave can operate as trans-
mitter or receiver but the master device determines
which mode is activated.
This Material Copyrighted by Its Respective Manufacturer
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