參數(shù)資料
型號(hào): 24C02CISN
英文描述: EconoRAM
中文描述: I2C串行EEPROM的
文件頁(yè)數(shù): 7/12頁(yè)
文件大?。?/td> 174K
代理商: 24C02CISN
24C02C
1999 Microchip Technology Inc.
DS21202C-page 7
6.0
WRITE OPERATIONS
6.1
Byte Write
Following the start signal from the master, the device
code(4 bits), the chip select bits (3 bits), and the R/W
bit which is a logic low is placed onto the bus by the
master transmitter. The device will acknowledge this
control byte during the ninth clock pulse. The next byte
transmitted by the master is the word address and will
be written into the address pointer of the 24C02C. After
receiving another acknowledge signal from the
24C02C the master device will transmit the data word
to be written into the addressed memory location. The
24C02C acknowledges again and the master gener-
ates a stop condition. This initiates the internal write
cycle, and during this time the 24C02C will not gener-
ate acknowledge signals (Figure 6-1). If an attempt is
made to write to the protected portion of the array when
the hardware write protection has been enabled, the
device will acknowledge the command but no data will
be written. The write cycle time must be observed even
if the write protection is enabled.
6.2
Page Write
The write control byte, word address and the first data
byte are transmitted to the 24C02C in the same way as
in a byte write. But instead of generating a stop condi-
tion, the master transmits up to 15 additional data bytes
to the 24C02C which are temporarily stored in the on-
chip page buffer and will be written into the memory
after the master has transmitted a stop condition. After
the receipt of each word, the four lower order address
pointer bits are internally incremented by one. The
higher order four bits of the word address remains con-
stant. If the master should transmit more than 16 bytes
prior to generating the stop condition, the address
counter will roll over and the previously received data
will be overwritten. As with the byte write operation,
once the stop condition is received an internal write
cycle will begin (Figure 6-2). If an attempt is made to
write to the protected portion of the array when the
hardware write protection has been enabled, the device
will acknowledge the command but no data will be writ-
ten. The write cycle time must be observed even if the
write protection is enabled.
6.3
WRITE PROTECTION
The WP pin must be tied to V
CC
or V
SS
. If tied to V
CC
,
the upper half of the array (080-0FF) will be write pro-
tected. If the WP pin is tied to V
SS
, then write opera-
tions to all address locations are allowed.
FIGURE 6-1:
BYTE WRITE
FIGURE 6-2:
PAGE WRITE
S
T
A
R
T
Note:
Page write operations are limited to writing
bytes within a single physical page, regard-
less of the number of bytes actually being
written. Physical page boundaries start at
addresses that are integer multiples of the
page buffer size (or ‘page size’) and end at
addresses that are integer multiples of
[page size - 1]. If a page write command
attempts to write across a physical page
boundary, the result is that the data wraps
around to the beginning of the current page
(overwriting data previously stored there),
instead of being written to the next page as
might be expected. It is therefore neces-
sary for the application software to prevent
page write operations that would attempt to
cross a page boundary.
S
P
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
A
R
T
S
T
O
P
CONTROL
BYTE
WORD
ADDRESS
DATA
A
C
K
A
C
K
A
C
K
S
P
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
CONTROL
BYTE
WORD
ADDRESS (n)
DATA n
DATA n + 15
S
T
O
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
DATA n +1
This Material Copyrighted by Its Respective Manufacturer
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