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參數資料
| 型號： | 24C01SCW |
| 英文描述： | SCSI Terminator |
| 中文描述： | I2C串行EEPROM的 |
| 文件頁數： | 4/12頁 |
| 文件大?。?/td> | 168K |
| 代理商： | 24C01SCW |
24C01SC/02SC
DS21170D-page 4
1999 Microchip Technology Inc.
2.0
FUNCTIONAL DESCRIPTION
The 24C01SC/02SC supports a bi-directional two-wire
bus and data transmission protocol. A device that
sends data onto the bus is defined as transmitter, and
a device receiving data as receiver. The bus has to be
controlled by a master device which generates the
serial clock (SCL), controls the bus access, and gener-
ates the START and STOP conditions, while the
24C01SC/02SC works as slave. Both master and slave
can operate as transmitter or receiver, but the master
device determines which mode is activated.
3.0
BUS CHARACTERISTICS
The following bus protocol has been defined:
Data transfer may be initiated only when the bus
is not busy.
During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
Accordingly, the following bus conditions have been
defined (Figure 3-1).
3.1
Bus not Busy (A)
Both data and clock lines remain HIGH.
3.2
Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.
3.3
Stop Data Transfer (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
3.4
Data Valid (D)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited, although only the last 16
will be stored when doing a write operation. When an
overwrite does occur, it will replace data in a first in first
out fashion.
3.5
Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
The device that acknowledges has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the last
byte that has been clocked out of the slave. In this case,
the slave must leave the data line HIGH to enable the
master to generate the STOP condition.
Note:
The 24C01SC/02SC does not generate
any acknowledge bits if an internal pro-
gramming cycle is in progress.
FIGURE 3-1:
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
SCL
SDA
(
A
)
(B)
(D)
(D)
(C)
(
A
)
START
CONDITION
ADDRESS OR
ACKNOWLEDGE
VALID
DATA
ALLOWED
TO CHANGE
STOP
CONDITION
This Material Copyrighted by Its Respective Manufacturer
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| 24C01SCW08 | SCSI Terminator |
| 24C01SCWF | I2C Serial EEPROM |
| 24C01SCWF08 | SCSI Terminator |
| 24C02SCS08 | 5V High-Speed RS-232 Transceivers with 0.1uF Capacitors |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| 24C01SC-W | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:24C01C-P 24C01C-IP 24C01C-EP 24C01C-SN 24C01C-ISN 24C01C-ESN 24C01C-ST 24C01C-IST 24C01C-EST |
| 24C01SCW08 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:I2C Serial EEPROM |
| 24C01SC-W08 | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:24C01C-P 24C01C-IP 24C01C-EP 24C01C-SN 24C01C-ISN 24C01C-ESN 24C01C-ST 24C01C-IST 24C01C-EST |
| 24C01SCWF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:I2C Serial EEPROM |
| 24C01SC-WF | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:24C01C-P 24C01C-IP 24C01C-EP 24C01C-SN 24C01C-ISN 24C01C-ESN 24C01C-ST 24C01C-IST 24C01C-EST |
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