參數(shù)資料
型號: 24AA174
英文描述: Serial EEPROM
中文描述: 串行EEPROM
文件頁數(shù): 8/12頁
文件大?。?/td> 160K
代理商: 24AA174
24AA174
DS21102F-page 8
1999 Microchip Technology Inc.
8.0
PIN DESCRIPTIONS
8.1
SDA Serial Address/Data Input/Output
This is a Bi-directional pin used to transfer addresses and
data into and data out of the device. It is an open drain ter-
minal, therefore the SDA bus requires a pullup resistor to
V
CC
(typical 10K
for 100 kHz, 1K
for 400 kHz).
For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are reserved
for indicating the START and STOP conditions.
8.2
SCL Serial Clock
This input is used to synchronize the data transfer from
and to the device.
8.3
WP
This pin must be connected to either V
SS
or V
CC
.
If tied to V
SS
, normal memory operation is enabled
(read/write the entire memory 000-7FF).
If tied to V
CC
, WRITE operations are inhibited. The
entire memory will be write-protected. Read opera-
tions are not affected.
This feature allows the user to use the 24AA174 as a
serial ROM when WP is enabled (tied to V
CC
).
8.4
A0, A1, A2
These pins are used to configure the proper chip
address in multiple-chip applications (more than one
24AA174 on the same bus). The levels on these pins
are compared to the corresponding bits in the slave
address. The chip is selected if the compare is true.
Up to eight 24AA174s may be connected to the same
bus. These pins must be connected to either V
SS
or V
CC
.
8.5
Security Access Control
The security row is enabled by sending the control
sequence with the I
2
C slave address of 0110. Bit 0 of
the control byte must be set to a one for a READ
OPERATION or a zero for the OTP WRITE OPERA-
TION. The SECURITY ACCESS DATA is always read
starting at byte 0 for N bytes up to and including byte
15. (See Figure 4-2).
8.6
Security Access Write
The S.A.W. data is written to the device using a normal
page write following the proper control access
sequence. Upon receiving the final stop bit, the internal
write sequence will commence. At the completion of
the internal write sequence a fuse will be set disabling
the write function for the 16 byte security page.
8.7
Security Access Read
The security access read is accomplished by executing
the normal read sequences, following the security
access control sequence with bit 0 set to a one. The
security page read starts at data byte 0.
Note:
The level on A1 is compared to the inverse
of the slave address.
FIGURE 8-1:
CURRENT ADDRESS READ
FIGURE 8-2:
RANDOM READ
CONTROL
BYTE
A
C
K
S
T
A
R
T
S
T
O
P
DATA n
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
A
C
K
N
O
S
1 A2 A1 A0 B2 B1 B0
P
S
P
S
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
A
R
T
S
T
O
P
CONTROL
BYTE
A
C
K
WORD
ADDRESS (n)
CONTROL
BYTE
S
T
A
R
T
DATA (n)
A
C
K
A
C
K
N
O
A
C
K
1 A2A1A0B2B1B0
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