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參數(shù)資料
| 型號(hào)： | 21C01SC |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | 1K 5.0V IIC serial EEPROMs for smart card(1K位,5.0V,ISO7816標(biāo)準(zhǔn),EEPROM) |
| 中文描述： | 一千5.0V進(jìn)口證的智能卡（每1000位和5.0V，符合ISO7816標(biāo)準(zhǔn)，EEPROM的串行EEPROM） |
| 文件頁(yè)數(shù)： | 3/12頁(yè) |
| 文件大小： | 84K |
| 代理商： | 21C01SC |
1996 Microchip Technology Inc.
Preliminary
DS21170A-page 3
24C01SC/02SC
TABLE 1-3:
AC CHARACTERISTICS
FIGURE 1-2:
BUS TIMING DATA
Parameter
Symbol
Min.
Max.
Units
Remarks
Clock frequency
F
CLK
—
400
kHz
Clock high time
T
HIGH
600
—
ns
Clock low time
T
LOW
1300
—
ns
SDA and SCL rise time
T
R
—
300
ns
(Note 1)
SDA and SCL fall time
T
F
—
300
ns
(Note 1)
START condition hold time
T
HD
:
STA
600
—
ns
After this period the first clock
pulse is generated
START condition setup time
T
SU
:
STA
600
—
ns
Only relevant for repeated
START condition
Data input hold time
T
HD
:
DAT
0
—
ns
(Note 2)
Data input setup time
T
SU
:
DAT
100
—
ns
STOP condition setup time
T
SU
:
STO
600
—
ns
Output valid from clock
T
AA
—
900
ns
(Note 2)
Bus free time
T
BUF
1300
—
ns
Time the bus must be free
before a new transmission can
start
Output fall time from V
minimum to V
IH
IL
maximum
T
OF
20 +0.1
CB
250
ns
(Note 1), CB
≤
100 pF
Input filter spike suppression
(SDA and SCL pins)
T
SP
—
50
ns
(Note 3)
Write cycle time
T
WR
—
10
ms
Byte or Page mode
Endurance
—
10
6
—
cycles
25
(Note 4)
°
C, Vcc = 5V, Block Mode
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined T
SP
and V
HYS
specifications are due to new Schmitt trigger inputs which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-
cation, please consult the Total Endurance Model which can be obtained on our BBS or website.
SCL
SDA
IN
SDA
OUT
T
HD
:
STA
T
SU
:
STA
T
F
T
HIGH
T
R
T
SU
:
STO
T
SU
:
DAT
T
HD
:
DAT
T
BUF
T
AA
T
HD
:
STA
T
AA
T
SP
T
LOW
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