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| 型號： | 21628 |
| 英文描述： | 1.8 Volt-only Flash Memory Technology |
| 中文描述： | 1.8伏只快閃記憶體技術(shù) |
| 文件頁數(shù)： | 6/9頁 |
| 文件大?。?/td> | 75K |
| 代理商： | 21628 |
1.8 Volt-only Flash Memory Technology Background
5
have severe negative impact on the read operation of the device in terms of reliability and
performance.
To achieve robust read operation, an approach similar to that used in the 2.7 volt-only devices
is taken. These devices utilize a dynamic circuit design approach. There are many advantages
to this approach, including high performance and reduced power consumption. For this
discussion, however, the main advantage is the limited time that elevated currents are required
to complete the read access. This allows use of very silicon-efficient booster circuits on the
wordline to provide the required control gate voltage. This enables the Super Low voltage
family to use the same proven, highly reliable memory cell structure as in the 5 volt-only and
2.7 volt-only device families. Operating at the same V
t
levels results in the same guaranteed
high endurance (1,000,000 cycles minimum). An additional benefit to the booster circuit is
the noise isolation it provides. The booster circuit essentially decouples the word line
allowing line levels to be tightly controlled during the access.
To achieve performance at 1.8 volts, a new thin gate oxide transistor is used in the peripheral
circuits. Reducing the gate oxide thickness from 150 down to 100 increases the
transconductance (gain) of these transistors while reducing their threshold voltage. The net
effect is to bring circuit operating currents up to a level consistent with the desired level of
performance and active power consumption.
The proven AMD flash memory cell structure and the innovative techniques discussed above
combine to deliver a highly reliable, high performance device capable of operating from a
single 1.8 volt supply.
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The Program operation deposits electrons (charge) on the cell’s floating gate. In AMD
devices, Channel Hot Electron injection (CHE) is the mechanism utilized. CHE depends on
imparting more kinetic energy to the channel electrons than can be transferred to the silicon
lattice, thus making them “hot.” In order for these electrons to make it onto the floating gate,
they need to become hot enough (gain enough energy) to overcome the tunnel oxide potential
barrier. Creating the environment for CHE requires a high bias on the control gate (8 V) and
elevated drain voltage (5 V). Reducing the external supply voltage presents an obvious
challenge.
A charge pump approach is utilized to support the CHE programming environment.
Generating the voltage levels required isn’t trivial, but the real issue is in managing the
current. Silicon efficient implementation demands maintaining a strict power budget. This is
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