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參數(shù)資料
| 型號(hào)： | 21050-AA |
| 英文描述： | PCI Bus Interface/Controller |
| 中文描述： | PCI總線接口/控制器 |
| 文件頁(yè)數(shù)： | 7/15頁(yè) |
| 文件大?。?/td> | 92K |
| 代理商： | 21050-AA |
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21050 PCI-to-PCI Bridge Hardware Implementation
Application Note
7
3.0
Clocking
The following sections provide an overview of 21050 clocking requirements, and explain how to
implement clocks using the 21050 on a motherboard and an option card.
3.1
21050 Clocking
The 21050 has two clocking domains, one for the primary PCI interface and one for the secondary
PCI interface. Both interfaces must operate at the same frequency and must be synchronous to each
other.
The primary clocking domain is controlled by the p_clk input.
The secondary bus arbiter pins and the data synchronization pins operate in the secondary interface
clocking domain. The secondary clocking domain is controlled by the s_clk input.
The relationship between the p_clk and s_clk inputs has the following restrictions:
Both interfaces must operate at the same frequency.
Maximum clock frequency is 33 MHz.
Maximum delay between p_clk and s_clk is 7 ns for both rising and falling edges.
Minimum delay between p_clk and s_clk is 0 ns, that is, s_clk cannot precede p_clk for both
rising and falling edges.
Input duty cycle of p_clk must be between 45–55%, measured at 1.5V.
3.2
21050 Output Clocks
The 21050 generates seven secondary bus clock outputs, s_clk_o<6:0>. These clocks are derived
from p_clk. Use one of the secondary clock outputs as the secondary clock input to the 21050, and
use the six other outputs for devices on the secondary bus.
These s_clk_o<6:0> clock outputs are generated directly from p_clk, and their relationship to p_clk
has the following restrictions:
All clock outputs must operate at the same frequency.
Maximum delay between p_clk and s_clk_o is 5 ns for both rising and falling edges.
Minimum delay between p_clk and s_clk_o is 0 ns for both rising and falling edges.
21050 skews the duty cycle by adding a maximum of 1.5 ns to clock high (and, therefore,
removing that same amount from clock low).
It is recommended that the 21050 secondary clock outputs not be used as primary clock inputs to
another 21050, because the 21050 can skew the duty cycle of the secondary clock outputs that it
generates. As a general rule, do not use the secondary clock outputs when the 21050 is
implemented on a motherboard, because a card containing another 21050 might be plugged into
one of the option card slots. However, you must use the 21050 secondary clock outputs when the
21050 is implemented on an option card.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 21052-AA | PCI Bus Interface/Controller |
| 21052-AB | PCI Bus Interface/Controller |
| 210600 | KABEL PROFI 3FACH KOAX 75 OHM SW 100M |
| 210602 | KABEL PROFI 3FACH KOAX 75 OHM GRAU 100M |
| 210E | Thermal Probe Multiplexer(熱探頭多路復(fù)用器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 21050AB | 功能描述:IC PCI-PCI BRIDGE 208QFP RoHS:否 類(lèi)別:集成電路 (IC) >> 接口 - 專(zhuān)用 系列:- 特色產(chǎn)品:NXP - I2C Interface 標(biāo)準(zhǔn)包裝:1 系列:- 應(yīng)用:2 通道 I²C 多路復(fù)用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類(lèi)型:表面貼裝 產(chǎn)品目錄頁(yè)面:825 (CN2011-ZH PDF) 其它名稱(chēng):568-1854-1 |
| 21050-AB | 制造商:Intel 功能描述:IC,BUS CONTROLLER,CMOS,QFP,208PIN |
| 21050D401R00JE | 制造商:OHMITE 制造商全稱(chēng):Ohmite Mfg. Co. 功能描述:Dividohm? Vitreous Enamel Adjustable Power |
| 21050D401R00KE | 制造商:OHMITE 制造商全稱(chēng):Ohmite Mfg. Co. 功能描述:Dividohm? Vitreous Enamel Adjustable Power |
| 21050D40250RJE | 制造商:OHMITE 制造商全稱(chēng):Ohmite Mfg. Co. 功能描述:Dividohm? Vitreous Enamel Adjustable Power |
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