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參數資料
| 型號： | 20463 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | SmartACFL Modem |
| 中文描述： | SmartACFL調制解調器 |
| 文件頁數： | 13/24頁 |
| 文件大?。?/td> | 210K |
| 代理商： | 20463 |
V.90/K56flex Modem Device Sets with SmartDAA Technology for Low Power Applications
SmartACFL
Doc. No. 100444A
Conexant
13
Proprietary Information
MDP (P9373) Hardware Pins and Signals
General
The major functional application signals are
summarized below.
System Control and Status
The following discrete signals are used by the host to
control and monitor MDP operation:
Wakeup Reset (WKRES#); input
Interrupt Request for MDP Interface (IRQ); output
Raw Ring (SSD_RING#); output
Ring Wake Reset (SSD_RINGWAKE#); output
SmartDAA Interrupt for SmartDAA Interface
(SSD_INT); output
Digital Speaker Interface
The following output is used for audible call progress
or carrier monitoring in Data/Fax mode only where
sound quality is not important.
Digital Speaker Output (DSPKOUT); output
Host Parallel Bus Interface
The parallel address, data, and control signals are:
Address Lines (A[6:0]); input
Data Lines (D[7:0]), input/output
Chip Select (CS#); input
Read Enable (READ#); input
Write Enable (WRITE#); output
Host Serial Data Interface
The serial data and clock signals are:
Receive Data (RXD); output
Receive Data Clock (RXCLK); output
Transmit Data (TXD); input
Transmit Data Clock (TXCLK); output
Host Serial Voice Interface (S models)
The serial data and clock signals are:
Serial Data Out (SI_DD); output
Serial Data In (SI_DU); input
Serial Shift Clock (SI_CLK); input
Sample Shift Clock (SI_FRAME); input
LSD Interface (Through DIB)
The DIB interface signals are:
Clock and Power Positive (PWRCLKP); output
Clock and Power Negative (PWRCLKN); output
Data Positive (DIB_DATAP); input/output
Data Negative (DIB_DATAN); input/output
VC Interface
The VC interface signals are:
Sleep (IASLEEP); output
Master Clock (M_CLK); output
Voice Serial Clock (V_SCLK); output
Voice Serial Control (V_CTRL); output
Voice Serial Frame Sync (V_STROBE); input
Voice Serial Transmit Data (V_TXSIN); output
Voice Serial Receive Data (V_RXOUT); input
MDP Signal Interface and Pin Assignments
The MDP (P9373) 100-pin TQFP hardware interface
signals are shown in Figure 5.
The MDP (P9373) 100-pin TQFP pin signals are
shown in Figure 6.
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