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參數(shù)資料
| 型號： | 20068 |
| 英文描述： | and Am29243? EH Controller Data Sheet |
| 中文描述： | 和Am29243？高血壓控制器數(shù)據(jù)表 |
| 文件頁數(shù)： | 10/36頁 |
| 文件大?。?/td> | 428K |
| 代理商： | 20068 |
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P R E L I M I N A R Y
10
Am29240 EH Microcontroller Series
(single and double precision) are defined for the proces-
sor; however, there is no direct hardware support for
these formats in the Am29240EH microcontroller series.
Protection
The Am29240EH microcontroller series offers two mutu-
ally exclusive modes of execution—the User and Super-
visor modes—that restrict or permit accesses to certain
processor registers and external storage locations.
The register file may be configured to restrict accesses
to Supervisor-mode programs on a bank-by-bank basis.
Memory Management Unit
The Am29240EH microcontroller series provides a
memory-management unit (MMU) for translating virtual
addresses into physical addresses. The page size for
translation ranges from 1 Kbyte to 16 Mbytes in powers
of 4. The Am29245EH and Am29240EH microcontrol-
lers each have a single, 16-entry TLB. The Am29243EH
microcontroller has dual 16-entry TLBs, each capable of
mapping pages of different size.
Interrupts and Traps
When the microcontroller takes an interrupt or trap, it
does not automatically save its current state information
in memory. This lightweight interrupt and trap facility
greatly improves the performance of temporary inter-
ruptions such as simple operating-system calls that re-
quire no saving of state information.
In cases where the processor state must be saved, the
saving and restoring of state information is under the con-
trol of software. The methods and data structures used to
handle interrupts—and the amount of state saved—may
be tailored to the needs of a particular system.
Interrupts and traps are dispatched through a 256-entry
vector table that directs the processor to a routine that
handles a given interrupt or trap. The vector table may
be relocated in memory by the modification of a proces-
sor register. There may be multiple vector tables in the
system, though only one is active at any given time.
The vector table is a table of pointers to the interrupt and
trap handlers, and requires only 1 Kbyte of memory. The
processor performs a vector fetch every time an inter-
rupt or trap is taken. The vector fetch requires at least
three cycles, in addition to the number of cycles required
for the basic memory access.
PIN DESCRIPTIONS
A23–A0
Address Bus (output, synchronous)
The Address Bus supplies the byte address for all ac-
cesses, except for DRAM accesses. For DRAM ac-
cesses, multiplexed row and column addresses are
provided on A14–A1. A2–A0 are also used to provide a
clock to an optional burst-mode EPROM.
BOOTW
Boot ROM Width (input, asynchronous)
This input configures the width of ROM Bank 0, so the
ROM can be accessed before the ROM configuration
has been set by the system initialization software. The
BOOTW signal is sampled during and after a processor
reset. If BOOTW is High before and after reset (tied
High), the boot ROM is 32 bits wide. If BOOTW is Low
before and after reset (tied Low), the boot ROM is 16 bits
wide. If BOOTW is Low before reset and High after reset
(tied to RESET), the boot ROM is 8 bits wide. This signal
has special hardening against metastable states, allow-
ing it to be driven with a slow-rise-time signal and permit-
ting it to be tied to RESET.
BURST
Burst-Mode Access (output, synchronous)
This signal is asserted to perform sequential accesses
from a burst-mode device.
CAS3–CAS0
Column Address Strobes, Byte 3–0
(output, synchronous)
A High-to-Low transition on these signals causes the
DRAM selected by RAS3–RAS0 to latch the column ad-
dress and complete the access. To support byte and
half-word writes, column address strobes are provided
for individual DRAM bytes. CAS3 is the column address
strobe for the DRAMs, in all banks, attached to
ID31–ID24. CAS2 is for the DRAMs attached to
ID23–ID16, and so on. These signals are also used in
other special DRAM cycles.
CNTL1–CNTL0
CPU Control
(input, asynchronous, internal pull-ups)
These inputs specify the processor mode: Load Test
Instruction, Step, Halt, or Normal.
DACKD–DACKA
DMA Acknowledge D through A
(output, synchronous)
These signals acknowledge an external transfer on a
DMA channel. DMA acknowledgments are not dedi-
cated to a particular DMA channel—each channel spec-
ifies which acknowledge line, if any, it is using. Only one
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