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參數(shù)資料
| 型號： | 1B21AN |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 3/8頁 |
| 文件大?。?/td> | 140K |
| 描述： | IC CONV V TO I HYBRID 38-DIP |
| 標準包裝： | 1 |
| 類型： | 電壓和電流控制器 |
| 全量程： | ±50ppm/°C |
| 線性： | ±0.02% |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 38-DIP（0.500"，12.70mm），8 引線 |
| 供應(yīng)商設(shè)備封裝： | 8-DIP |
| 包裝： | 管件 |
1B21
Rev. C | Page 3 of 8
SPECIFICATIONS
Typical at +25癈 and V
S
= ?5 V, unless otherwise noted.
Table 1.
Parameter
Specification
INPUT SPECIFICATIONS
Input Range
0 V to + 10 V
Full-Scale Input
+1 V min to +10 V max
Input Bias Current
?0 pA (?00 pA max)
OUTPUT SPECIFICATIONS
Current Output Range
4 mA to 20 mA, 0 mA to 20 mA
Load Compliance at VLOOP = 30 V
27 V min
Max Output Current @ Input Overload
25 mA
Output Noise, 100 Hz Bandwidth
1 糀 p-p
NONLINEARITY (% of Span)
?.02% (?.05% max)
ISOLATION
CMV, Input to Output Continuous
1500 V rms
CMR @ 60 Hz
90 dB min
Transient Protection
IEEE-STD 472 (SWC)
ACCURACY
Warm-Up Time to Rated Performance
5 min
Total Output Error @ +25癈 (Untrimmed)
Offset (V
IN
= 0 V)
1
?00 糀
Span (VIN = +10 V)
?.6% FSR
vs. Temperature (25癈 to +85癈)
Offset
2
?00 nA/癈
Span
?0 ppm/癈
REFERENCE OUTPUT
Voltage
+6.225 V dc
Output Error
?.0% max
Temperature Coefficient
?5 ppm/癈 typ
DYNAMIC RESPONSE
Settling Time to 0.1% of FS for 10 V Step
9 ms
Small Signal Bandwidth
100 Hz
POWER SUPPLY
Input Side
Operating Voltage
?5 V ?%
Quiescent Current
+15 V Supply
10 mA
15 V Supply
5 mA
Power Supply Rejection
?.01% V
Loop Side
Operating Voltage
+15 V to +30 V
Maximum Current
25 mA
ENVIRONMENTAL
Temperature Range
Rated Performance
25癈 to +85癈
Operating
40癈 to +85癈
Storage
40癈 to +85癈
Relative Humidity, Noncondensing
0 to 95% @ +60癈
CASE SIZE
0.7 ?2.1 ?0.35
(17.8 ?53.3 ?8.9) mm
1
For 0 mA to 20 mA mode. For 4 mA to 20 mA mode, an additional 60 糀 is contributed by the ?.0% reference error on the 4 mA output.
2
For a complete discussion of the temperature effects of the offset resistor and reference, refer to the
section.
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