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參數(shù)資料
| 型號： | 17S100LSI |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Spartan Family of One-Time Programmable Configuration PROMs |
| 中文描述： | Spartan系列一次性可編程配置PROM的 |
| 文件頁數(shù)： | 2/9頁 |
| 文件大?。?/td> | 107K |
| 代理商： | 17S100LSI |
Spartan Family of One-Time Programmable Configuration PROMs (XC17S00)
2
www.xilinx.com
1-800-255-7778
DS030 (v1.8) October 10, 2001
Product Specification
R
Pin Description
Controlling PROMs
Connecting the Spartan device with the PROM:
The DATA output of the PROM drives the D
IN
input of
the lead Spartan device.
The Master Spartan device CCLK output drives the
CLK input of the PROM.
The RESET/OE input of the PROM is driven by the
INIT output of the Spartan device. This connection
assures that the PROM address counter is reset before
the start of any (re)configuration, even when a
reconfiguration is initiated by a V
CC
glitch. Other
methods
—
such as driving RESET/OE from LDC or
system reset
—
assume that the PROM internal
power-on-reset is always in step with the FPGAs
internal power-on-reset, which may not be a safe
assumption.
The CE input of the PROM is driven by the DONE
output of the Spartan device, provided that DONE is
not permanently grounded. Otherwise, LDC can be
used to drive CE, but must then be unconditionally
High during user operation. CE can also be
permanently tied Low, but this keeps the DATA output
active and causes an unnecessary supply current of
10 mA maximum.
FPGA Master Serial Mode Summary
The I/O and logic functions of the Configurable Logic Block
(CLB) and their associated interconnections are established
by a configuration program. The program is loaded either
automatically upon power up, or on command, depending
on the state of the Spartan device MODE pin. In Master
Serial mode, the Spartan device automatically loads the
configuration program from an external memory. The Spar-
tan PROM has been designed for compatibility with the
Master Serial mode.
Upon power-up or reconfiguration, the Spartan device
enters the Master Serial mode when the MODE pin is Low.
Data is read from the PROM sequentially on a single data
line. Synchronization is provided by the rising edge of the
temporary signal CCLK, which is generated during configu-
ration.
Table 1:
Spartan PROM Pinouts
Pin Name
8-pin
PDIP and
VOIC
20-pin
SOIC
Pin Description
DATA
1
1
Data output, High-Z state when either CE or OE are inactive. During programming,
the DATA pin is I/O. Note that OE can be programmed to be either active High or
active Low.
CLK
2
3
Each rising edge on the CLK input increments the internal address counter, if both
CE and OE are active.
RESET/OE
(OE/RESET)
3
8
When High, this input holds the address counter reset and puts the DATA output in
a high-impedance state. The polarity of this input pin is programmable as either
RESET/OE or OE/RESET. To avoid confusion, this document describes the pin as
RESET/OE, although the opposite polarity is possible on all devices. When RESET
is active, the address counter is held at zero, and the DATA output is in a
high-impedance state. The polarity of this input is programmable. The default is
active High RESET, but the preferred option is active Low RESET, because it can
be driven by the FPGAs INIT pin.
The polarity of this pin is controlled in the programmer interface. This input pin is
easily inverted using the Xilinx HW-130 programmer software. Third-party
programmers have different methods to invert this pin.
CE
4
10
When High, this pin disables the internal address counter, puts the DATA output in
a high-impedance state, and forces the device into low-I
CC
standby mode.
GND
5
11
GND is the ground connection.
V
CC
7, 8
18, 20
The V
CC
pins are to be connected to the positive voltage supply.
Notes:
1.
Pins not listed in the table are reserved and
must
not be externally connected.
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