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參數(shù)資料
| 型號： | 17S100AVQI |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Spartan-II/Spartan-IIE Family OTP Configuration PROMs |
| 中文描述： | Spartan-II/Spartan-IIE家庭檢察官辦公室配置PROM的 |
| 文件頁數(shù)： | 3/9頁 |
| 文件大?。?/td> | 91K |
| 代理商： | 17S100AVQI |
Spartan-II/Spartan-IIE Family OTP Configuration PROMs (XC17S00A)
DS078 (v1.8) November 18, 2002
Advance Product Specification
www.xilinx.com
1-800-255-7778
3
R
Pinout Diagrams
Controlling PROMs
Connecting the Spartan device with the PROM:
The DATA output of the PROM drives the D
IN
input of
the lead Spartan device.
The Master Spartan device CCLK output drives the
CLK input of the PROM.
The RESET/OE input of the PROM is connected to the
INIT pin of the Spartan device and a pull-up resistor.
This connection assures that the PROM address
counter is reset before the start of any
(re)configuration, even when a reconfiguration is
initiated by a V
CC
glitch.
The CE input of the PROM is connected to the DONE
pin of the Spartan device and a pull-up resistor. CE can
also be permanently tied Low, but this keeps the DATA
output active and causes an unnecessary supply
current of 10 mA maximum.
FPGA Master Serial Mode Summary
The I/O and logic functions of the Configurable Logic Block
(CLB) and their associated interconnections are established
by a configuration program. The program is loaded either
automatically upon power up, or on command, depending
on the state of the Spartan device mode pins. In Master
Serial mode, the Spartan device automatically loads the
configuration program from an external memory. The
XC17S00A PROM has been designed for compatibility with
the Master Serial mode.
Upon power-up or reconfiguration, the Spartan device
enters the Master Serial mode when the mode pins are set
to Master Serial mode. Data is read from the PROM
sequentially on a single data line. Synchronization is pro-
vided by the rising edge of the temporary signal CCLK,
which is generated during configuration.
Master Serial mode provides a simple configuration inter-
face (
Figure 1
). Only a serial data line, two control lines, and
a clock line are required to configure the Spartan device.
Data from the PROM is read sequentially, accessed via the
internal address and bit counters which are incremented on
every valid rising edge of CCLK.
If the user-programmable, dual-function D
IN
pin on the
Spartan device is used only for configuration, it must still be
held at a defined level during normal operation. The
Spartan-II/Spartan-IIE
family
automatically with an on-chip pull-up/down resistor or
keeper circuit.
takes
care
of
this
PD8/
VO8
Top View
DS078_04_111502
8
7
6
5
1
2
3
4
VCC
VCC
NC
GND
DATA (D0)
CLK
OE/RESET
CE
DS078_05_111502
SO20
Top View
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
DATA(D0)
NC
CLK
NC
NC
NC
NC
OE/RESET
NC
CE
VCC
NC
VCC
NC
NC
NC
NC
NC
NC
GND
1
2
3
4
5
6
7
8
9
10
11
VQ44
Top View
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
N
O
N
C
N
N
G
N
N
N
N
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
N
C
N
G
D
N
V
N
N
V
N
DS073_06_101002
4
4
4
4
4
3
3
3
3
3
3
33
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