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參數(shù)資料
| 型號： | 17512LJC |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Serial Configuration PROMs |
| 中文描述： | 串行配置PROM的 |
| 文件頁數(shù)： | 1/10頁 |
| 文件大?。?/td> | 72K |
| 代理商： | 17512LJC |
December 10, 1997 (Version 1.1)
5-1
Features
On-chip address counter, incremented by each rising
edge on the clock input
Simple interface to the FPGA; requires only one user
I/O pin
Cascadable for storing longer or multiple bitstreams
Programmable reset polarity (active High or active Low)
for compatibility with different FPGA solutions
Supports XC4000EX/XL fast configuration mode (15.0
MHz)
Low-power CMOS Floating Gate process
Available in 5 V and 3.3 V versions
Available in compact plastic packages: 8-pin PDIP,
20-pin SOIC, and 20-pin PLCC.
Programming support by leading programmer
manufacturers.
Design support using the Xilinx Alliance and
Foundation series software packages.
Description
The XC1701L, XC1701 and XC17512L serial configuration
PROMs (SCPs) provide an easy-to-use, cost-effective
method for storing Xilinx FPGA configuration bitstreams.
When the FPGA is in master serial mode, it generates a
configuration clock that drives the SCP. A short access time
after the rising clock edge, data appears on the SCP DATA
output pin that is connected to the FPGA DIN pin. The
FPGA generates the appropriate number of clock pulses to
complete the configuration. Once configured, it disables the
SCP. When the FPGA is in slave mode, the SCP and the
FPGA must both be clocked by an incoming signal.
Multiple devices can be concatenated by using the CEO
output to drive the CE input of the following device. The
clock inputs and the DATA outputs of all SCPs in this chain
are interconnected. All devices are compatible and can be
cascaded with other members of the family.
For device programming, either the Xilinx Alliance or Foun-
dation series development system compiles the FPGA
design file into a standard Hex format, which is then trans-
ferred to the programmer.
0
XC1701L
(3.3V),
XC1701
(5.0V) and
XC17512L
(3.3V)
Serial Configuration PROMs
December 10, 1997 (Version 1.1)
0
5*
Product Specification
Figure 1: Simplified Block Diagram (does not show programming circuit)
EPROM
Cell
Matrix
Address Counter
CE
RESET/
OE or
OE/
RESET
DATA
CEO
OE
Output
CLK
V
CC
V
PP
GND
X3185
TC
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