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參數(shù)資料
| 型號： | 1725 |
| 廠商： | Linear Technology Corporation |
| 英文描述： | General Purpose Isolated Flyback Controller |
| 中文描述： | 通用隔離反激式控制器 |
| 文件頁數(shù)： | 19/28頁 |
| 文件大?。?/td> | 241K |
| 代理商： | 1725 |
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19
LT1725
1725f
Output Impedance Error
An additional error source is caused by transformer sec-
ondary current flow through the real life nonzero imped-
ances of the output rectifier, transformer secondary and
output capacitor. Because the secondary current only
flows during the off portion of the duty cycle, the effective
output impedance equals the “DC” lumped secondary
impedance times the inverse of the off duty cycle. If the
output load current remains relatively constant, or, in less
critical applications, the error may be judged acceptable
and the feedback resistor divider ratio adjusted for nomi-
nal expected error. In more demanding applications, out-
put impedance error may be minimized by the use of the
load compensation function (see Load Compensation).
MINIMUM LOAD CONSIDERATIONS
The LT1725 generally provides better low load perfor-
mance than previous generation switcher/controllers uti-
lizing indirect output voltage sensing techniques.
Specifically, it contains circuitry to detect flyback pulse
“collapse,” thereby supporting operation well into discon-
tinuous mode. Nevertheless, there still remain constraints
to ultimate low load operation. These relate to the mini-
mum switch on time and the minimum enable time.
Discontinuous mode operation will be assumed in the
following theoretical derivations.
As outlined in the Operation section, the LT1725 utilizes a
minimum output switch on time, t
ON
. This value can be
combined with expected V
IN
and switching frequency to
yield an expression for minimum delivered power.
Minimum Power
f
L
V
t
V
I
PRI
IN
ON
OUT
OUT
=
(
)
=
1
2
2
This expression then yields a minimum output current
constraint:
I
f
L
V
V
t
OUT MIN
(
PRI
OUT
IN
ON
)
=
(
)
1
2
2
where
f = switching frequency
L
PRI
= transformer primary side inductance
V
IN
= input voltage
V
OUT
= output voltage
t
ON
= output switch minimum on time
An additional constraint has to do with the minimum
enable time. The LT1725 derives its output voltage infor-
mation from the flyback pulse. If the internal minimum
enable time pulse extends beyond the flyback pulse, loss
of regulation will occur. The onset of this condition can be
determined by setting the width of the flyback pulse equal
to the sum of the flyback enable delay, t
ED
, plus the
minimum enable time, t
EN
. Minimum power delivered to
the load is then:
Minimum Power
f
L
V
t
t
V
I
SEC
OUT
EN
ED
OUT
OUT
=
+
(
)
[
]
=
1
2
2
Which yields a minimum output constraint:
I
f V
L
t
t
OUT MIN
(
OUT
SEC
ED
EN
)
=
+
(
)
1
2
2
where
f = switching frequency
L
SEC
= transformer secondary side inductance
V
OUT
= output voltage
t
ED
= enable delay time
t
EN
= minimum enable time
Note that generally, depending on the particulars of input
and output voltages and transformer inductance, one of
the above constraints will prove more restrictive. In other
words, the minimum load current in a particular applica-
tion will be either “output switch minimum on time”
constrained, or “minimum flyback pulse time” constrained.
(A final note—L
PRI
and L
SEC
refer to transformer induc-
tance as seen from the primary or secondary side respec-
tively. This general treatment allows these expressions to
be used when the transformer turns ratio is nonunity.)
APPLICATIOU
W
U
U
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