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參數(shù)資料
| 型號： | 1417H4A |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | TRANSCEIVER, PDFO |
| 文件頁數(shù)： | 4/10頁 |
| 文件大小： | 189K |
| 代理商： | 1417H4A |
Lucent Technologies Inc.
3
Data Sheet
NetLight 1417G4A and 1417H4A
January 2000
ATM/SONET/SDH Transceivers
Electrostatic Discharge
Caution: This device is susceptible to damage as
a result of electrostatic discharge (ESD).
Take proper precautions during both
handling and testing. Follow
EIA* Stan-
dard
EIA-625.
Although protection circuitry is designed into the
device, take proper precautions to avoid exposure to
ESD.
Lucent employs a human-body model (HBM) for ESD
susceptibility testing and protection-design evaluation.
ESD voltage thresholds are dependent on the critical
parameters used to dene the model. A standard HBM
(resistance = 1.5 k
, capacitance = 100 pF) is widely
used and, therefore, can be used for comparison pur-
poses. The HBM ESD threshold established for the
1417G4A and 1417H4A transceivers is
±1000 V.
Application Information
The 1417 receiver section is a highly sensitive ber-
optic receiver. Although the data outputs are digital
logic levels (PECL), the device should be thought of as
an analog component. When laying out system applica-
tion boards, the 1417 transceiver should receive the
same type of consideration one would give to a sensi-
tive analog component.
Printed-Wiring Board Layout Consider-
ations
A ber-optic receiver employs a very high gain, wide
bandwidth transimpedance amplier. This amplier
detects and amplies signals that are only tens of nA in
amplitude when the receiver is operating near its sensi-
tivity limit. Any unwanted signal currents that couple
into the receiver circuitry cause a decrease in the
receiver's sensitivity and can also degrade the perfor-
mance of the receiver's signal detect (SD) circuit. To
minimize the coupling of unwanted noise into the
receiver, careful attention must be given to the printed-
wiring board layout.
At a minimum, a double-sided printed-wiring board
(PWB) with a large component-side ground plane
beneath the transceiver must be used. In applications
that include many other high-speed devices, a multi-
layer PWB is highly recommended. This permits the
placement of power and ground on separate layers,
which allows them to be isolated from the signal lines.
*
EIA is a registered trademark of Electronic Industries Association.
Multilayer construction also permits the routing of sen-
sitive signal traces away from high-level, high-speed
signal lines. To minimize the possibility of coupling
noise into the receiver section, high-level, high-speed
signals such as transmitter inputs and clock lines
should be routed as far away as possible from the
receiver pins.
Noise that couples into the receiver through the power
supply pins can also degrade performance. It is
recommended that the pi lter, shown in Figure 2, be
used for both the transmitter and receiver power
supplies.
Data and Signal Detect Outputs
The data and signal detect outputs of the 1417 trans-
ceiver are driven by open-emitter NPN transistors,
which have an output impedance of approximately 7
.
Each output can provide approximately 50 mA maxi-
mum current to a 50
load terminated to VCC – 2.0 V.
Due to the high switching speeds of ECL outputs,
transmission line design must be used to interconnect
components. To ensure optimum signal delity, both
data outputs (RD+/RD–) should be terminated identi-
cally. The signal lines connecting the data outputs to
the next device should be equal in length and have
matched impedances. Controlled impedance stripline
or microstrip construction must be used to preserve the
quality of the signal into the next component and to
minimize reections back into the receiver, which could
degrade its performance. Excessive ringing due to
reections caused by improperly terminated signal
lines makes it difcult for the component receiving
these signals to decipher the proper logic levels and
can cause transitions to occur where none were
intended. Also, by minimizing high-frequency ringing,
possible EMI problems can be avoided.
The signal-detect output is positive ECL (PECL) logic
for the 1417G4A and TTL for the 1417H4A. A logic low
at this output indicates that the optical signal into the
receiver has been interrupted or that the light level has
fallen below the minimum signal detect threshold. This
output should not be used as an error rate indicator,
since its switching threshold is determined only by the
magnitude of the incoming optical signal.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 1417H4A(NETLIGHT) | 制造商:AGERE 制造商全稱:AGERE 功能描述:ATM/SONET/SDH Transceivers |
| 1417H5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FIBER OPTIC TRANSCEIVER |
| 1417H5A | 制造商:AGERE 制造商全稱:AGERE 功能描述:NetLight 1417G5 and 1417H5-Type ATM/SONET/SDH Transceivers with Clock Recovery |
| 1417H5-TYPE(NETLIGHT) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ATM/SONET/SDH Transceivers with Clock Recovery |
| 1417K4A | 制造商:NL 功能描述: |
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