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參數資料
| 型號： | 12C672 |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | Test Prod Wire; Conductor Size AWG:18; No. Strands x Strand Size:65 x 36; Jacket Color:Black; Conductor Material:Copper; Jacket Material:Rubber; Leaded Process Compatible:Yes; Number of Conductors:1; Outer Diameter:0.144" RoHS Compliant: Yes |
| 中文描述： | EPROM存儲器編程規(guī)范 |
| 文件頁數： | 4/14頁 |
| 文件大?。?/td> | 175K |
| 代理商： | 12C672 |
PIC12C67X and PIC12CE67X
DS40175A-page 4
1998 Microchip Technology Inc.
2.2
Program/Verify Mode
The program/verify mode is entered by holding pins
GP1 and GP0 low while raising MCLR pin from V
V
IHH
(high voltage). VDD is then raised from VIL to
VIH.Once in this mode the user program memory and
the configuration memory can be accessed and pro-
grammed in serial fashion. The mode of operation is
serial, and the memory that is accessed is the user pro-
gram memory. GP1 is a Schmitt Trigger input in this
mode.
The sequence that enters the device into the program-
ming/verify mode places all other logic into the reset
state (the MCLR pin was initially at V
that all I/O are in the reset state (High impedance
inputs).
IL
to
IL
). This means
1.0.1
PROGRAM/VERIFY OPERATION
The GP1 pin is used as a clock input pin, and the GP0
pin is used for entering command bits and data
input/output during serial operation. To input a com-
mand, the clock pin (GP1) is cycled six times. Each
command bit is latched on the falling edge of the clock
with the least significant bit (LSB) of the command
being input first. The data on pin GP0 is required to
Note 1:
The MCLR pin must be raised from V
V
IHH
before V
DD
is applied. This is to
ensure that the device does not have the
PC incremented while in valid operation
range.
Do not power GP2, GP4 or GP5 before
V
DD
is applied.
IL
to
Note 2:
have a minimum setup and hold time (see AC/DC
specs) with respect to the falling edge of the clock.
Commands that have data associated with them (read
and load) are specified to have a minimum delay of 1
between the command and the data. After this delay
the clock pin is cycled 16 times with the first cycle being
a start bit and the last cycle being a stop bit. Data is
also input and output LSB first. Therefore, during a
read operation the LSB will be transmitted onto pin
GP0 on the rising edge of the second cycle, and during
a load operation the LSB will be latched on the falling
edge of the second cycle. A minimum 1
specified between consecutive commands.
All commands are transmitted LSB first. Data words
are also transmitted LSB first. The data is transmitted
on the rising edge and latched on the falling edge of the
clock. To allow for decoding of commands and reversal
of data pin configuration, a time separation of at least
1
μ
s is required between a command and a data word
(or another command).
The commands that are available are listed
in Table 1-1.
μ
s
μ
s delay is also
1.0.1.1
LOAD CONFIGURATION
After receiving this command, the program counter
(PC) will be set to 0x2000. By then applying 16 cycles
to the clock pin, the chip will load 14-bits a “data word”
as described above, to be programmed into the config-
uration memory. A description of the memory mapping
schemes for normal operation and configuration mode
operation is shown in Figure 2-1. After the configuration memory is entered, the only way to get back to the user pro-
gram memory is to exit the program/verify test mode by taking MCLR low (V
IL
).
TABLE 1-1:
COMMAND MAPPING
Command
Mapping (MSB ... LSB)
Data
Load Configuration
Load Data
Read Data
Increment Address
Begin programming
End Programming
0
0
0
0
0
0
0, data(14), 0
0, data(14), 0
0, data(14), 0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
1
1
0
0
0
1
0
0
0
0
0
1
1
1
0
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